Firmware Design Research Articles

Software-Bus-Toolchain (SBT): Introducing a Versatile Method for Quickly Implementing (I)IoT-Scenarios

The Internet of Things (IoT) has become ubiquitous. IoT devices are applied in a multitude of applications, e.g., in smart home scenarios, building automation, smart energy and smart cities, healthcare, and industrial environments. Fast and efficient implementation and roll-out of IoT devices is a critical factor for successs and acceptance of IoT devices. At the same time, the variety of hardware platforms that can be used for IoT applications, as well as the number of IoT orchestration platforms is increasing. Finding the right combination of tooling and hardware is not trivial, but essential for building applications that provide value. In this work, a Software-Bus-Toolchain (SBT) is introduced that encapsulates firmware design, data point definition, and communication protocol usage. Furthermore, an IoT control platform is provided to control and evaluate the IoT modules. Thus, using the SBT, solely the business logic has to be designed, while the hardware-design is automated to a high degree. Usage of the Zephyr framework allows the interchange of hardware modules, while interfaces provide easy adaption of data points and communication capabilities. The implementation of interfaces to the IoT-platform as well as to the communication layer provides a universal usage of logic and data elements. The SBT is evaluated in two application scenarios, where its flexible nature is shown.

Multifrequency Electrical Impedance Tomography Images for Swine Pneumonia Detection Using Conductivity Differences

This article introduces a new MfEIT UDESC Mark I system, which consists of a 32-electrode setup featuring a modified Howland current source, low cost, portability, and non-radiation. The system is capable of reconstructing electrical conductivity tomographic images at a rate of 30.624 frames per second, taking about 5 min for imaging. The current source employs a 0.5 mA adjacent current application pattern with frequencies ranging from 10 kHz to 1 MHz. This article outlines the hardware, firmware, and software design specifications, which include the design of the current source, calibration procedures, and image reconstruction process. Tomographic images of conductivity were reconstructed in ex vivo healthy pig lungs and those with pneumonia, as a proof of concept for future applications in live pigs. The high spectral power density, combined with real-time system calibration provides clinical advantages in veterinary medicine. The goal is to identify lung areas affected by Mycoplasma hyopneumoniae in pigs through the analysis of electrical conductivity difference, offering a valuable tool to assist veterinarians to obtain images of respiratory diseases. The modified reconstruction method GREIT (EIDORS) was evaluated with experimental data and was compared with the Gauss–Newton and Total Variation methods, where GREIT 2D proved to be superior.

LabOSat-02: Hardware and Firmware Development of an On-Board Computer for Small Satellites

LabOSat is an applied research group whose main goal is to increase the Technology Readiness Level of electronic devices and systems for their use in space. To achieve this objective, the group designs and fabricates satellite payloads. Between 2014 and 2020 LabOSat has participated in 9 missions in orbit. In recent years, LabOSat started the development of LabOSat-02, a payload controller designed for small satellites. In this brief communication, LabOSat-02 hardware and firmware design is described and presented.

Towards digital twins for safety demonstrations: Interfacing strategies for FPGA-targeted applications

For facilitating a framework of digital twins for safety demonstrations, this research paper identifies feasible interfacing strategies to connect a digital twin of novel all-electric actuation systems with safety-critical functions targeted for an FPGA device. The framework can improve safety demonstrations with a lifecycle perspective and one-to-one twinning if the values of the framework are realizable. For selecting a suitable interfacing strategy, the paper proposes five performance criteria to preserve the framework’s values while interfacing the controller logic with a digital twin. The paper introduces a safety-critical case study, thereby establishing reasoning, literature, and simulation testing of the interfacing strategies regarding relevant interfacing considerations and the performance criteria. We recommend using behavioral models during the design of FPGA firmware and commercial tools for verification against a reference model during the synthesizing steps. For the final development stage, we propose an FPGA-based digital twin, which offers high computational speed, scalability for integration testing, and comprehensive testing of the digital logical circuits. Implementing the recommendation requires practical implications, including adhering to FPGA configuration constraints and developing custom resources for interacting with the FPGA-based digital twin.

Noninvasive Fuel Flow Monitoring System for Vented Fuel Oil Heaters.

In this work, we present hardware and firmware design and preliminary testing results for a noninvasive device for measuring fuel oil consumption in fuel oil vented heaters. Fuel oil vented heaters are a popular space heating method in northern climates. Monitoring fuel consumption is useful to understanding residential daily and seasonal heating patterns and understanding the thermal characteristics of buildings. The device is a pump monitoring apparatus (PuMA) that employs a magnetoresistive sensor to monitor the activity of solenoid driven positive displacement pumps, which are commonly used in fuel oil vented heaters. PuMA accuracy for calculating fuel oil consumption was evaluated in a lab setting and found to vary up to 7% from the measured consumption value during testing. This variance will be explored more in field testing.

Hardware and Firmware Design and Implementation of Twin 8-Bit and 32-Bit Microcontroller Boards for Research and Educational Applications

This document describes the design and implementation sequence of hardware and firmware components of two microcontroller boards of 8-bit and 32-bit architectures, which use similar form factors and share common input/output devices and recently developed web-based user interfaces. These developments are the result of over two decades of experimentation in educational and research measurement systems in renewable energy projects. The boards are intended to fill a gap between low-cost hobby systems and high-end research loggers, especially where international standards require control of uncertainties, as is the case with small wind turbine power curve assessments. The focus was to increase reliability in the hardware aspects and make software development easier by including user-friendly firmware and a set of in-house C language coding rules for new developments and refactoring of legacy code. Testing of the low-level driver sections and the use of automated tools such as Ceedling for higher-level module testing are also described.

Design of High-Speed Data Transmission System Based on USB 3.0

The development of high-speed and high-precision ADC promotes the development process of waveform digitization in nuclear physics, which in turn brings the digitization process forward. Waveform digitizer preserves the complete pulse waveform data for reconstruction, placing greater demands on data transmission speed. This paper introduces an optimized data transmission implementation routine based on USB 3.0. A complete USB transmission system design includes USB firmware design, FPGA logic design, and upper USB controller design. The software and hardware of the system are specially designed to realize high-speed bidirectional communication between FPGA and PC. Through actual test, USB 3.0 transmission is high-speed and reliable, which solves a key problem of data transmission and storage of digitizer. This study has promising applications in nuclide measurements.

QiCells: A Modular RFSoC-based Approach to Interface Superconducting Quantum Bits

Quantum computers will be a revolutionary extension of the heterogeneous computing world. They consist of many quantum bits (qubits) and require a careful design of the interface between the classical computer architecture and the quantum processor. For example, even single nanosecond variations of the interaction may have an influence on the quantum state. Designing a tailored interface electronics is therefore a major challenge, both in terms of signal integrity with respect to single channels, as well as the scaling of the signal count. We developed such an interface electronics, an RFSoC-based qubit control system called QiController. In this article, we present the modular FPGA firmware design of our system. It features so-called digital unit cells, or QiCells. Each cell contains all the logic necessary to interact with a single superconducting qubit, including a custom-built RISC-V-based sequencer. Synchronization and data exchange between the cells is facilitated using a special star-point structure. Versatile routing and frequency-division multiplexing of generated signals between QiCells and converters are also supported. High-level programmability is provided using a custom Python-based description language and an associated compiler. We furthermore provide the resource utilization of our design and demonstrate its correct operation using an actual superconducting five-qubit chip.

ПРОГРАММНО-АППАРАТНОЕ МОДЕЛИРОВАНИЕ КОМПЛЕКСИРОВАННОЙ ИНЕРЦИАЛЬНОЙ НАВИГАЦИОННОЙ СИСТЕМЫ НАЗЕМНОГО ОБЪЕКТА

The purpose of this paper is creation of an efficient software and hardware model of a groundmobile object navigation system. Simulation process is one of the key instruments for engineering solutionsdevelopment at all stages of a complex technical system lifecycle. Navigation system model describedin this paper is software-hardware by nature and is implemented as software modules that supporthardware interaction with each other. The described system of ground object navigation systemsimulation has been developed in the course of several design projects and scientific research works.The developed model of a ground mobile object navigation system includes several programming units.Each of these units simulates the operation process as close as possible to the original. Internal andexternal interaction interfaces and navigation system communication protocols are also simulated withthe account for real object operation cyclograms. It should be noted that one of the main advantages ofa software simulation over a developmental testing or breadboarding is the opportunity to perform aprofound analysis of operation algorithms without the use of any additional resources. At the same time,it is often necessary to perform firmware design in order to make the simulation process identical withthe real operation. The process of navigation system architecture simulation allows performing a comparativeanalysis of several base components sets and their interaction patterns. Such comparison resultsin an optimal system structure providing the information user with navigation data in the mostefficient way. The paper determines basic simulation process tasks. The simulation stage may becomecrucial for complex systems design as it may aid achieving the best technical result. The proposed structure,key elements of a ground navigation simulation system and approaches to their interaction arrangementhave been approved in the course of several research and development works. At the sametime, it was found that the validity of developed models and their compliance to simulated units allowsperforming a highly reliable navigation system analysis. The developed software-hardware model allowedprocessing telemetry records obtained under different product operation conditions, performingtheir analysis and developing engineering solutions that increase the efficiency of navigation systems.

The DAQPATH readout system of the Serenity boards for the CMS Phase-II Upgrade

The Serenity boards are ATCA custom boards used in the readout of the Phase-II CMS detector. Each board can handle up to 144 optical serial links (up to 25Gb/s each) and supports up to two high-performance FPGAs. In several applications the Serenity board is required to aggregate raw events (Front-End data) from the detector at every Accepted Level 1 trigger and route this event fragment to the central DAQ system. The architecture and behavior of the DAQPATH firmware that collects and merges Front-End data and manages their transmission to the DAQ system over 25Gb/s output optical links are here described. • Data, trigger, readout electronics for HEP CMS experiment. • High speed links communication. • HDL firmware design.

Design and Development of a Low-cost Integrated Dosimeter for External Beam Dosimetry in Radiation Oncology.

Radiation dosimeters play a crucial role in radiation oncology by accurately measuring radiation dose, ensuring precise and safe radiation therapy. This study presents the design and development of a low-cost printed circuit board (PCB) dosimeter and an integrated electrometer with sensitivity optimized for dose rates intended for use in megavoltage radiation therapy. The PCB dosimeter was designed in KiCad, and it uses a low-cost S5MC-13F general-purpose 1 kV 5A power diode as a radiation detector. The dosimeter is calibrated against a known dose derived from an ionization chamber and tested for dose linearity, dose rate dependence, field size dependence, and detector orientation dependence. The observed average dose differences between the delivered and measured doses for most measurements were found to be < 1.1%; the dose rate linearity between 100 MU/min and 1400 MU/min was found to be within 1.3%. This low-cost architecture could successfully be adapted further for a scalable, cost-effective dosimetry solution through firmware or circuit design.

Hardware Implementation Study of Particle Tracking Algorithm on FPGAs

In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%.

PCI-Express Based High-Speed Readout for the Belle II DAQ Upgrade

Belle II is a new-generation B-factory experiment, dedicated to exploring new physics beyond the standard model of elementary particles in the flavor sector. Belle~II started data-taking in April 2018, using a synchronous data acquisition (DAQ) system based on pipelined trigger flow control. The Belle II DAQ system is designed to handle a 30-kHz trigger rate with approximately 1% of dead time, under the assumption of a raw event size of 1 MB. The DAQ system is reliable, and the overall data-taking efficiency reached 84.2% during the run period of January 2020 to June 2020. The current readout system cannot be operated in the term of 10 years from the viewpoint of DAQ maintainability; meanwhile, the readout system is obstructing high-speed data transmission. A solution involving a PCI-express-based readout module with high data throughput of up to 100 Gb/s was adopted to upgrade the Belle II DAQ system. We particularly focused on the design of firmware and software based on this new generation of readout board, called PCIe40, with an Altera Arria 10 field-programmable gate array chip. Forty-eight GBT (GigaBit Transceiver) serial links, PCI-express hard IP-based DMA architecture, interface of timing and trigger distribution system, and slow control system were designed to integrate with the current Belle II DAQ system. This paper describes the performances accomplished during the data readout and slow control tests conducted using a test bench and a demonstration performed using on-site front-end electronics, specifically involving Belle II TOP and KLM sub-detectors.

A Device Performance Data Acquisition System Based on Data Fusion Method

The data acquisition system is a system which collects the analog signal from the sensor, converts it into digital signal, then sends it to the computer for processing, and outputs the processing results in the form of demand. Based on the research of USB technology, this paper describes a data acquisition system based on data fusion technology, including hardware design, firmware design, device driver design and host application design. In the part of hardware design, this paper first describes the performance and characteristics of data acquisition chip, FPGA and USB2.0 interface chip, and then gives the specific hardware design scheme. In the part of firmware design, this paper first introduces the firmware architecture of FX2, and then introduces the firmware design of GPIF interface mode in detail. In the driver development part, this paper first introduces the WDM driver development model, and then completes the USB device driver design of the data acquisition system. Finally, the device performance data acquisition system based on data fusion method is completed with driver.

ImpediSense:A long lasting wireless wearable bio-impedance sensor node

Bio-impedance is a method to assess the body composition safely, non-invasively and inexpensively. This method finds application for assessing body fluid and body composition for multiple disease scenarios in clinical environments and for at-home monitoring of chronic ailments. Bio-impedance sensors require higher power than most other bio-signal acquisition systems due to need of high frequency current and voltage management. Currently used bio-impedance devices are bulky due to incorporation of large batteries and cannot be used for long term monitoring, especially for wearable applications. This limits the widespread implementation of bio-impedance measurement devices. We present the design and implementation of a wireless wearable bio-impedance sensor node, ImpediSense, which has a low power system design that achieves long duration operability without compromising on sensor measurement accuracy and precision. Experimental evaluation show a battery life of several months for measuring bio-impedance with power duty cycling every 1 min over ten frequencies in the range of 10 kHz–100 kHz, using a small form factor 250 mA h Li-ion battery. The lifetime is achieved due to several power optimization implemented in system design of hardware and firmware resulting in active power of 53 mW and idle power of 15.7 μW. Additionally, the presented sensor node shows high performance in terms of accuracy of impedance measurement with an error less than 1.5 % and precision of 0.6 Ω when measuring tetrapolar bio-impedance of the human body. With the inclusion of a small sized battery, ImpediSense has a compact form factor with dimensions 3 cm × 1.8 cm × 0.6 cm, making it more conducive for incorporation in wearable systems.

Design and Implementation Scheme of QSFP28 Optical Transceiver for Long-Reach Transmission Using PAM4 Modulation

A quad, small form-factor pluggable 28 Gbps optical transceiver design scheme is proposed. It is capable of transmitting 50 Gbps of data up to a distance of 40 km using modulation signals with a level-four pulse-amplitude. The proposed scheme is designed using a combination of electro-absorption-modulated lasers, transmitter optical sub-assembly, low-cost positive-intrinsic-native photodiodes, and receiver optical sub-assembly to achieve standard performance and low cost. Moreover, the hardware and firmware design schemes to implement the optical transceiver are presented. The results confirm the effectiveness of the proposed scheme and the performance of the manufactured optical transceiver, thereby confirming its applicability to real industrial sites.

Real-Time Extensive Livestock Monitoring Using LPWAN Smart Wearable and Infrastructure

Extensive unsupervised livestock farming is a habitual technique in many places around the globe. Animal release can be done for months, in large areas and with different species packing and behaving very differently. Nevertheless, the farmer’s needs are similar: where livestock is (and where has been) and how healthy they are. The geographical areas involved usually have difficult access with harsh orography and lack of communications infrastructure. This paper presents the design of a solution for extensive livestock monitoring in these areas. Our proposal is based in a wearable equipped with inertial sensors, global positioning system and wireless communications; and a Low-Power Wide Area Network infrastructure that can run with and without internet connection. Using adaptive analysis and data compression, we provide real-time monitoring and logging of cattle’s position and activities. Hardware and firmware design achieve very low energy consumption allowing months of battery life. We have thoroughly tested the devices in different laboratory setups and evaluated the system performance in real scenarios in the mountains and in the forest.

Safer- Self Propelling Baby Jogger with Obstacle Avoidance using Zigbee Technology

The current pandemic situation has forced people to (WFH) work from home and it has become very difficult to provide constant monitoring and entertainment to the small babies. Even the playschools and baby creche are closed due to the current situation of Covid 19, the parents are finding it difficult to maintain the baby at home safely even in a jogger or stroller. In this paper, we are introducing a prototype design for a self-propelling baby jogger to avoid the obstacle, using Zigbee technology. The prototype uses a self-propelling baby stroller automated with ultrasonic sensors and Zigbee, which alerts the system to handle the safer movement of the stroller. The combination of firmware and hardware makes the entire system operational for the controlled movements of the baby jogger. The system design consists of three parts such as hardware design for the circuit, firmware design for programming the microcontroller and, an application for an Android phone to control the jogger using Zigbee. Ultrasonic sensors detect the obstacles and prevent the stroller from crashing it. Bearing some good implementation at home, it has many more interesting applications on road/public places. Environment being more rigorous and riskier, strollers can work to its purpose.

Gesture Recognition With Ultrasounds and Edge Computing

The aim of this work is to prove that it is possible to develop a system able to detect gestures based only on ultrasonic signals and Edge devices. A set of 7 gestures plus idle has been defined, being possible to combine them to increase the recognized gestures. In order to recognize them, Ultrasound transceivers will be used to detect the 2 dimensional gestures. The Edge device approach implies that the whole data is processed in the device at the network edge rather than depending on external devices or services such as Cloud Computing. The system presented in this paper has been proven to be able to measure Time of Flight (ToF) signals that can be used to recognize multiple gestures by the integration of two transceivers, with an accuracy between 84.18% and 98.4%. Due to the optimization of the preprocessing correlation technique to extract the ToF from the echo signals and our specific firmware design to enable the parallelization of concurrent processes, the system can be implemented as an Edge Device.

Development of a Colorimetric Sensor for Autonomous, Networked, Real-Time Application

This review describes an ongoing effort intended to develop wireless sensor networks for real-time monitoring of airborne targets across a broad area. The goal is to apply the spectrophotometric characteristics of porphyrins and metalloporphyrins in a colorimetric array for detection and discrimination of changes in the chemical composition of environmental air samples. The work includes hardware, software, and firmware design as well as development of algorithms for identification of event occurrence and discrimination of targets. Here, we describe the prototype devices and algorithms related to this effort as well as work directed at selection of indicator arrays for use with the system. Finally, we review the field trials completed with the prototype devices and discuss the outlook for further development.