FIR Filter Design Research Articles

Design and implementation of low power multiplierless FIR filters on FPGA and ASIC

ABSTRACT This paper presents a low-power design and implementation approach for multiplierless FIR filters by reducing switching activity between filter coefficients using different optimisation algorithms. The objective function simultaneously minimises hamming distance between the consecutive filter coefficients, passband, and stopband ripples. Low-pass, high-pass, band-pass, and band-stop FIR filters of different order and word lengths are designed using improved grey-wolf optimisation. Comparison with grey-wolf optimisation, hybrid particle swarm optimisation, and grey-wolf optimisation, and whale optimisation algorithms is performed for different statistical parameters. The proposed filter is also compared with existing filter designs and shows considerable improvement in design metrics. For low-power implementation of designed FIR filters, carry-save-adder trees are utilised. FPGA and ASIC platforms are used for implementation. Basys-3 (Artix-7) FPGA board is targeted using the Vivado tool for FPGA implementation. Hardware design metrics such as slice LUTs, slice registers, slices, and dynamic power consumption are obtained. ASIC implementation is also performed using the Cadence Genus tool for a 45 nm Nan gate open cell library and total area, power, and delay are reported. The obtained results for FPGA slice utilisation and power consumption provide an average reduction of 61.39% and 74.13%, respectively. ASIC implementation provides an average 58.60% reduction in area-power product.

Optimal design of digital FIR filters based on text convolutional neural network for aliasing errors reduction in FI-DAC

Optimal design of digital FIR filters based on text convolutional neural network for aliasing errors reduction in FI-DAC

Optimizing Energy-Efficient in VLSI Architecture for FIR Filter in Seismic Signal Processing

This project aims to developing an optimized and energy-efficient VLSI design for FIR filters specifically designed for seismic signal processing. The process begins by converting seismic signal dataset values into binary format, and then, simulating them in MATLAB, and generating a coefficient file. This coefficient file is then analyzed using Verilog HDL code and simulated in the Xilinx Vivado 2022.2 tool to assess key parameters such as area, delay, and power. The suggested architecture lessens the complexity of computing, hardware efficiency compared to traditional FIR filters that utilize the CSE technique. This design employs a critical method known as the CSD-based Matrix-Grouped Common Subexpression Elimination (MCSE) algorithm, which significantly reduces the quantity of logic operators (LOs) and logic depths (LDs). Additionally, the design incorporates a Half-Unit Biased (HUB) rounding technique to minimize the truncation errors and cut-set retiming method to reduce the critical-path delay (CPD). This hardware-efficient FIR filter constructs integrates the CSD-based MCSE algorithm, HUB rounding, and cut-set retiming techniques to offer a reconfigurable FIR filter configuration optimized for hardware efficiency, thereby enhancing the real-time alert seismic signal processing. The implementation of an Artix-7 FPGA board including clock gating techniques to further reduces the power consumption.

Convex Optimization Based Design of FIR Filters for Reference Shaping

Abstract This paper explores design of Finite Impulse Response filters for controlling underdamped systems while dealing with uncertainties in model parameters. By setting magnitude constraints in the frequency domain within a convex programming framework, it ensures that dominant resonant modes are attenuated at the end of the maneuver, high-frequency unmodeled modes are not excited, and there is no inordinate accentuation of frequencies in the passband of the filter. A mobile platform with an attached flexible beam serves as a testbed to validate the designs for rest to rest maneuvers, demonstrating how different cost functions of error between the desired and optimized magnitude response affect the filter performance. The study also examines robustness in the notch area by shifting the natural frequencies of the system by shifting a tip mass at the free end of the beam. The total energy at the final maneuver time of the first three system modes is calculated as a vibration suppression metric and is used to compare established input shapers with the proposed Finite Impulse Response filters.

Multibeam Wideband Transmit Beamforming Using 2D Sparse FIR Trapezoidal Filters

A low-complexity multibeam wideband transmit beamformer using a 2D sparse FIR filter design capable of multiple beams is proposed as a digital building block for fully digital beamformers. The 2D sparse FIR filter has multiple trapezoid-shaped passbands pertaining to wideband beams aimed at particular directions. The proposed multibeam digital beamformer drives a uniform linear array of wideband antenna elements to achieve the wideband multibeam transmit-mode signals desired by the communication system. The 2D sparse FIR filter is designed to be optimal in the minimax sense using convex optimization techniques. Full-wave electromagnetic simulations using real antenna models confirm that the proposed wideband transmit beamformer can achieve multibeam transmission in the 1.3–2.8 GHz frequency range, with more than 70% fractional bandwidth. Furthermore, the adoption of the wideband transmit multibeam beamformer leads to a significant reduction in digital arithmetic (computational) complexity compared with previously reported wideband transmit beamformers of similar transfer function type, without deteriorating beam directionality and causing increases in the side-lobe level. The proposed sparse 2D FIR multibeam beamformer architecture is well-suited for both sub-6 GHz (legacy) band transmit beamforming, frequency range three (FR3) beamforming up to 28 GHz, and mmWave operation for emerging 5G/6G applications.

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

Impedance cardiography (ICG) is a rapidly growing non-invasive cardiac health monitoring approach. Synchronous detection of ICG requires an FIR filter to remove the high-frequency carrier signal. Low power consumption and compact area are critical considerations in the design of portable biomedical systems. This paper proposes a novel product quantization-based optimization strategy for the Urdhva Tiryagbhyam Sutra-based multiplier architecture. This paper presents an ASIC design of a low-power and low-area 64th-order programmable FIR filter architecture using the optimized Urdhva Tiryagbhyam Multiplier. The programmable architecture empowers medical practitioners to select the carrier frequency at which the ICG analysis will be performed. The elimination of redundant multipliers from the design based on the filter coefficients is demonstrated. The programmable Vedic FIR filter architecture (described in VHDL) is implemented on the Basys-3 FPGA board for rapid prototyping. The RTL-to-GDSII flow has been completed using Cadence digital design and sign-off tools for the SCL-180 nm technology. The results indicate that the proposed filter architecture occupies 41.33% less area and 42.16% lower power consumption than the contemporary designs described in the literature.

A New Design of Low Hardware Cost and Low Power Programmable FIR Filters

A New Design of Low Hardware Cost and Low Power Programmable FIR Filters

Design of Even-Order Variable Fractional Delay FIR Filters based on Pivot Element Weighting Iterative Algorithm

Design of Even-Order Variable Fractional Delay FIR Filters based on Pivot Element Weighting Iterative Algorithm

Improved Meta-Heuristic Technique to FIR Filter Design and Application

Improved Meta-Heuristic Technique to FIR Filter Design and Application

An algorithm for the design of optimal finite wordlength FIR filters

In practical FIR digital filter applications it is often necessary to represent the filter coefficients with a finite number of bits. The finite wordlength coefficient restriction reduces the filter quality and increases the filter deviation. This increase can be reduced substantially if the optimal finite wordlength coefficients are used. Computing these coefficients is more difficult and can be slow. It was shown before that the computation time can be significantly reduced with the help of a lower bound on the deviation increase. Derivation of a new algorithm that uses a much better lower bound is the purpose of this paper. We consider the general case of a length N filter with a discrete set of allowable real coefficients and demonstrate the effectiveness of the new algorithm on a set of filter design cases. The results show that this algorithm reduces the computation times up to 3 times when compared with the previously best results.

Review of Cosine Sum Window Functions and Recent Advances in FIR Filter Design Methods

Review of Cosine Sum Window Functions and Recent Advances in FIR Filter Design Methods

Comparative Analysis of FIR Filter Design using Different Multipliers and CLA adder

Comparative Analysis of FIR Filter Design using Different Multipliers and CLA adder

L1-Norm and LMS Based Digital FIR Filters Design Using Evolutionary Algorithms

L1-Norm and LMS Based Digital FIR Filters Design Using Evolutionary Algorithms

A Stable IIR Filter Design Approach for High-Order Active Noise Control Applications

In commercial non-adaptive active noise control (ANC) applications, an IIR filter structure is often used to reduce real-time computations. On the contrary, an FIR filter structure is usually preferred in the filter design phase because the FIR filter design formulation can be convex and is simple to solve. To combine the benefits of both FIR and IIR filter structures, one common approach in ANC applications is to use an IIR filter structure to fit a pre-designed FIR filter. However, to ensure stability, most of the common IIR filter fitting approaches involve the computation and relocation of poles which can be difficult for high-order cases. In this current work, a stable IIR filter design approach that does not need the computation and relocation of poles is improved to be applicable in ANC applications. The results demonstrate that the proposed method can achieve better fitting accuracy and steady-state noise control performance in high-order non-adaptive applications when the pre-designed noise control FIR filter is fitted. Besides fitting the noise control filter, the proposed method can also be used to fit the secondary path and acoustic feedback path to reduce the required real-time computations if adaptive controllers are applied.

Design and Performance Analysis of RNS-Based Reconfigurable FIR Filter for Noise Removal in Speech Signals Applications

In DSP solutions, the Residual Number System with Two's Complement systems is the most commonly utilized system for building low-power and high-throughput programmable Finite Impulse Response filters. It would be done by creating FIR filters in the Residual Number organization and 2's Enhance scheme by comparing the results to the current assert. The RNS based on FIR filter architecture reduces power consumption while allowing the device to operate at 150 MHz without increasing its size significantly. In case of memory and latency reduction, the implementations of the Residual Number System and 2's Complement System must be able to obtain and decode signals with fewer physical servers for every clock signal. The principal idea of this proposed model is to provide data bits with larger sizes for RNS-based multiplier and delayed wavelet LMS (DWLMS) that operates at speed high with premised reconfigurable FIR via forward and reverse conversions that don't produce as much power output and size as reflective thinking. The Application Specific Integrated Circuit will be designed and integrated for 32 nm technology. The proposed design addresses the four essential parameter optimization, such as power, area, and timing, using the Residual Number System, which is superior to Two's Complement System. According to the findings, there is a 13 percent reduction in power, a 21 % enhancement in area, and a 13 % enhance in throughput.

A new design methodology for window‐based FIR filters

AbstractThis letter describes a novel window‐based approach to FIR filter design. The window is constructed on the use of equispaced Gaussian basis functions. Unlike other known window‐based methods that do not allow for a satisfactory degree of control over band edges, the proposed method affords very good solution for controlling critical frequencies. In addition, the proposed window method is easier to implement than Kaiser's and affords a better passband flatness than any known design approach. It also yields stopband attenuations and control of critical frequencies which turn out to be very close to those obtainable with Parks–McClellan's method. So the proposed GBR window approach appears to be a significant step forward.

Design of FIR Filter Using Low-Power and High-Speed Carry Select Adder for Low-Power DSP Applications

Adders are one of the basic arithmetic circuits of any processor, microcomputer, multiplication circuits, etc. Presently, the most substantial areas in the research of VLSI design are area, power, and efficient high-speed circuits. In this paper two new architectures Carry Select Adder (CSLA) using D-latch and CSLA using multiplexers are proposed to reduce the power, delay, and its efficiency is compared with conventional carry select adder (CSLA) and existing literature. Architectural level power reduction is the most important area where it plays a vital role in improving the speed and power of the overall circuit. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm technology node is used for the design and implementation. The values obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency. For the proposed architectures, the evaluation results show that 60%–75% improvement in delay and 22%–56%in power when compared to other architectures. Proposed architectures shows increment in area but overall are delay product reduces compares to existing designs The proposed CSLA-DLATCH-FIR obtained significant reduction for 16-bits for power (46.4 (µW)), delay (0.66), ADP (359.8 × 10–15), and PDP (30.63 × 10–15). While the proposed CSLA-MUX-FIR has attained substantial performance for power (52.44 (µW)), delay (0.82 ns), ADP (457.392 × 10–15), and PDP (42.9 × 10–15). With the use of this proposed CSLA, a FIR filter was able to significantly reduce its power and delay.

Optimal design of digital FIR filters based on back propagation neural network

Optimal design of digital FIR filters based on back propagation neural network

2-D lossless FIR filter design using synthesis of the paraunitary transfer function matrix

2-D lossless FIR filter design using synthesis of the paraunitary transfer function matrix

High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design

Digital FIR Filters plays a major role in many signal processing applications. Generally, these filters are designed with multipliers and adders to find the filter output. This paper acquaints how to reduce the complexity of higher order FIR filter by using performance optimization techniques like retiming and pipelining. The filter’s throughput, energy efficiency, and latency, as well as the complexity of its technology, all need to be improved. By adopting pipelining technique, the arithmetic processes of addition and multiplication are separated. The break addition procedure is retimed. The architecture of Pipelining and Retiming with m-tap filters and n-bit word lengths were designed. The smallest delay achieved by the proposed distributed arithmetic-based FIR Filter with pipelining was 2.564ns for a 4tap implementation receiving an 8bit input, while the largest delay achieved was 56.04ns for a 64-tap implementation receiving a 32-bit word length. Delays as low as 0.68ns for a 4-tap implementation receiving an 8-bit input and as high as 4.53ns for a 64tap implementation receiving a 32bit word length have been achieved by using the suggested distributed arithmetic-based FIR Filter with retiming approach. Delay has been reduced by 73.2% for 4tap with 8bit input and by 91.9% for 64tap with 32bit word length compared to the pipelining approach.