Fast Fourier Transform Design Research Articles

Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

AbstractA new approach for implementing the fast Fourier transform (FFT) using complex binary number system (CBNS) is presented in this paper. The advantage of using CBNS is that instead of processing the real and imaginary parts of a complex number separately, we can process both as a single entity. A total of four FFT architectures have been developed, which are 16‐, 64‐, 256‐, and 1024‐point FFT architectures. The proposed FFT is designed using Verilog‐HDL and implemented using a Virtex‐7 field‐programmable gate array (FPGA). The maximum clock rate achieved by the proposed FPGA‐based design is 376.1 MHz. The FPGA resource utilization of the FFT is less than the state‐of‐the‐art FFT designs. An application‐specific integrated circuit (ASIC) for the FFT is also designed. The normalized energy per FFT of the proposed ASIC is 0.14 nJ, and the normalized area per FFT of the ASIC is 1.08 mm2 which is less than other existing designs.

FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement

The super-resolution (SR) method has been widely used to improve the resolution and quality of natural images, and it is currently being employed in medical imaging. Recently, many techniques have been introduced by researchers to improve the resolution and quality of the image. However, these approaches generate blurring and jagged edges in images. Hence, this article introduces novel deep learning (DL) with a fast Fourier transform (FFT) based intelligent approach (IA) to improve the quality and resolution of the image. A convolutional neural network (CNN) is emphasized for quality enhancement and resolution to recover lost information during image acquisition. This work undergoes three significant stages: de-noising, segmentation, and resolution improvement of the noisy input image. The double density discrete wavelet transform (DDDWT) technique is introduced to remove the noise and improve the visual image’s quality. Finally, the image resolution and quality enhancement are done using CNN with overlap and add (OA)-FFT based Wallace tree multiplier-red deer optimization (WT-RDO) technique. In the experimental scenario, the quality enhancement and image resolution outcome achieved accuracy of 97 % and 98 %, precision of 97 % and 97 %, sensitivity of 96 % and 98 %, specificity of 96 % and 98 %, PSNR of 30 dB and 26 dB, structural similarity index (SSIM) of 0.86 and 0.85, mean square error (MSE) of 0.01, mean absolute error (MAE) of 0.8, the time complexity of 61, power of 0.08 W, delay of 0.6 ns and throughput of 3.2 MB/s.

Energy Efficient Design of Fast Fourier Transform using Reversible Logic

Digital computation using reversible logic has gained significant research interest in recent years. It promises energy-efficient digital systems due to its information lossless characteristics. A thorough physical design of computationally intensive circuits is essential to analyze the true potential of this developing paradigm. This paper presents a reversible logic implementation of the Fast Fourier Transform (FFT) algorithm as a relevant design case. The proposed architecture’s hierarchical design is based on a reversible standard cell approach. CMOS 0.35μm technology is used for the pass transistor design as well as the full custom layout. Post layout simulations and technology design rule checks are used to validate all design units. The reversible design of an 8-point FFT with 8-bit quantization occupies 0.768 mm2 area and consumes 6.5 mW power at 10 MHz frequency and 3.3 V supply voltage. The major functional units of proposed FFT architecture demonstrate a considerable power saving as compared to their various existing implementations.

Design and Implementation of AGU based FFT Pipeline Architecture

Present it is most needful task to get various applications with parallel computations by using a Fast Fourier Transform (FFT) and the derived outputs should be in regular format. This can be achieved by using an advanced technique called Multipath delay commutator (MDC) Pipelining FFT processor and this processor will be capable to perform the computation of a different data streams at a time. In this paper the design and implementation of AGU based Pipelined FFT architecture is done Caluclation of a butterfly is done within 2 cycles by the instructions proposed. A Data Processing Unit (DPU) is employed in this pipeline architecture and supports the instructions & an FFT Adress Generation Unit (FAGU) caluclates butterfly input & output data adresses automatically. The DPU proposed sysyem requires less area compared to commericial DSP chips. Futhermore, the proposed FAGU reduces the number of FFT computation cycles. The FFT design architecture will have real data paths. With various FFT sizes, different radix & various parallesim levels, the FFT can be mapped to the pipeline architecture. The most attractive feature of the pipelined FFT architecture is it consists of bit reversal operation so it requires little number of registers and better throughput.

Impact of TMR design layouts on single event tolerance in SRAM-based FPGAs

For highly reliable applications in mission critical systems, the Triple Modular Redundancy (TMR) technique is believed to be a common and effective approach to mitigate Single Event Upsets (SEUs) in Field Programmable Gate Arrays (FPGAs). In one of our neutron test campaigns, we observed an increase of 53.8% in single event tolerance of our optimized Fast Fourier Transform (FFT) design compared with the baseline (i.e., the traditional FFT design), while the increase of the TMR'd optimized FFT design is only 30.8% compared with the baseline. Although it is believed that Multiple-Cell Upsets (MCUs) poses a negative impact on the single event performance of TMR, the results of the TMR'd optimized FFT design are far from our expectations. A large number of preliminary simulations confirm that layout changes have a significant impact on the Multiple-Bit Upsets (MBUs) sensitivity of TMR'd design. This is because in the layout obtained through automatic placement and routing, these replicated modules of the TMR are interlaced with each other. Therefore, MBUs are more likely to induce domain-crossing events and affect two or more TMR modules. To further harden the TMR'd design, either putting three identical circuits of the TMR'd design into three independent blocks or using Dynamic Partial Reconfiguration (DPR) is demonstrated effective in mitigating MBUs in Static Random-Access Memory (SRAM)-based FPGAs.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

PurposeThis paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.Design/methodology/approachA new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.FindingsWith the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.Originality/valueThis is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems

Fast Fourier Transform (FFT) processor is a paramount signal processing component in MIMO-OFDM wireless communication systems. Furthermore, novel applications introduced in 5G incur much more rigorous requirements for FFT designs including complexity, latency, and re-configurability. This paper presents the VLSI architecture design and circuit implementation of a FFT processor that is jointly optimized for low-latency, low-complexity, and configurability. Specifically, the proposed architecture processes two data streams concurrently and supports power-of-two FFT sizes from 64 to 2048 symbols. Moreover, a novel data-processing sequence is presented so that data streams are processed in a time-multiplexing manner and an efficient hardware-sharing architecture can be designed. In addition, a highly efficient I/O reorder mechanism is proposed so that the memory elements are shared between processing stages and the efficiency for utilizing memory components is enhanced. Based on the architectural optimizations, two FFT processors are realized. The ultra-low latency design achieves a latency of 4 μs with 41% area reduction compared to the comparable designs. On the other hand, the ultra-low complexity structure achieves a latency of 25 μs with 24% area reduction compared to the state-of-the-art implementations.

Design of High Speed FFT using UrdhvaTiryagbhyam Algorithm and Karatsuba Algorithm

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.

A Low-Overhead FFT Design With Higher SEU Resilience Implemented in FPGA

For area and power constraint applications in mission critical systems, the traditional fast Fourier transform (FFT) design requires huge hardware resources for data processing. In this article, we, therefore, present a low-overhead radix-2 FFT design that reduces hardware resources by simplifying the first two stages of the butterfly computations. Both the proposed design and the traditional design have been implemented in the MicroZus-20 (XC7Z020) platform. Their single-event performances have been compared through both fault injections and neutron exposure, and the experimental results demonstrate that the proposed design reduces the soft error rate by 53.8%. Also, the proposed FFT reduces the hardware resource consumption and circuit area by 64.8% when compared with the traditional design.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Two Parallel Pipelined FFT Architecture After Third Stage for Low Complexity and Latency

Complexity is the major issue in the development of pipelined Fast Fourier Transform (FFT) structure. A novel parallel pipelined FFT design constructed for low complexity and Latency. The proposed structure efficiently uses pipeline and parallel pipeline in the design. The first three stages of the structure follow the pipelining and from fourth stage there are two parallel paths simultaneously compute four complex additions, the first three single path stages that reduces complexity, parallel pipeline stages at the end of structure also reduces the Latency. The proposed structure is an optimized solution to reduce the trade-off between Latency and complexity. The comparative performance of the proposed structure with several other existing structures shows that it has Low latency with small cost of hardware.

ASIC design of 4K-point RADIX-2 FFT in 0.18 µm CMOS technology

Discrete Fourier transform (DFT) and inverse DFT are the key elements in the orthogonal frequency division multiplexing (OFDM) transmitter and receiver blocks, to represent changing signals in time and frequency domain. Fast Fourier transform (FFT), due to its high efficiency of computation over DFT, is currently used for many high-speed and real-time applications in both wireless and communication fields. In this paper, an application specific integrated circuit (ASIC) of 4k-point decimation in time (DIT) radix-2 FFT using fixed-point arithmetic has been designed. Finally, ASIC design results of various stages involved regarding area, timing and power consumption are presented.

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

Reconfigurable Multi-Butterfly Parallel Radix-r FFT Processor

The design of reconfigurable multi-butterfly parallel radix-r FFT (Fast Fourier Transform) processors is proposed. FFT is widely used in signal processing, and the application needs real-time and high performance, while most of the traditional designs are limited to the power of two, which wastes the buffers and multipliers in big data. In response to the problem, we improve the parallel FFT algorithm with the design of reconfigurable control machine combined with buffer/multiplier, and the cost function with the input of radix/number/paddling number/time consuming is deduced. Constrained with the number of buffer and multipliers, the radix and number can be computed with the optimum cost function, and the resolution space of computing performance and hardware cost is presented. The proposed guarantees the real-time performance with better flexibility compared with the previous literature, and the comparison also suggests the effectiveness of the design.

DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER

An efficient Fast Fourier Transform (FFT) algorithm is used in the Orthogonal Frequency Division Multiplexing (OFDM) applications in order to compute the discrete Fourier transform. Also, a Single Path Delay Feedback (SDF) which is pipeline FFT architecture is used for faster performance to achieve high throughput. In conventional method, the FFT design has high delay and power due to time taken by the multiplication part. To decrease the delay, Kogge Stone Parallel Prefix Adder (KSPPA) is used with booth multiplier. As SDF is a simpler approach to realize FFT in different length, 64-point Radix-4 SDF-FFT algorithm using KSPPA in the booth multiplier is discussed in this study. The system is implemented in Xilinx 12.4 ISE and simulated using MODELSIM 6.3c. Results show that the system reduces the delay and power.

DESIGN OF A HIGH-SPEED HIGH-ACCURACY 2048-POINT FFT USING SINGLE-PRECISION FLOATING-POINT ADAPTIVE CORDIC ON FPGA

In this paper, hardware design of a Fast Fourier Transform (FFT) core using Single-precision Floating-point Adaptive CORDIC is implemented on Altera Stratix IV FPGA. With FFT implementation, CORDIC is utilized for reducing the speed drawback of complex multiplication and the adaptive algorithm is proposed to decrease the iterations of conventional CORDIC. The experimental results of Adaptive CORDIC and 2048-point Radix-2 Multi-path Delay Commutator FFT designs are built and verified based on three kinds of Look-up Table that cost 16, 8 and 4 constant angles. As experimental results, there is a resource equivalence while it has a trade-off between speed performance and accuracy. In comparison, an adaptive CORDIC core based on Look-up Table of 16 constant angles, and 2048-point Radix-2 Multi-path Delay Commutator Fast Fourier Transform based on Adaptive CORDIC using Look-up Table of 16 constant angles are well responding to resource optimization, high-speed performance and high-accuracy of computations.

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications

This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture, supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design concept is mainly based on combined radix-5, radix-32, and radix24 single-path delay feedback FFT design approaches. In addition, in order to elaborate our hardware design, we also develop three design techniques, such as reconfigurable processing kernel with seven types (RPK-ST), efficient FIFO management scheme, and single-table approximation method. In an ASIC implementation with TSMC 40-nm CMOS technology, our 46-mode reconfigurable FFT chip only occupies a core area of 0.36 mm2, dissipates 48.46 mW, and operates up to clock frequency of 500 MHz. As compared with the other state-of-the-art works, our work delivers high-quality design results in the aspects of area- and energy-related performance indexes, providing a constructive FFT design prototyping for 3GPP-LTE systems.

Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design

In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and predictable memory access patterns, and it can be efficiently exploited for memory customization using eDRAM. The memory customization approaches are applied to both of the pipelined and memory-based FFT architectures. In the pipelined architecture, the read wordline (RWL) coupling write assist and data packing schemes are employed to reduce the redundant RWL and wordline driving, respectively, in column-interleaved memory arrays. The memory address decoder is also simplified with thermometer code by exploiting the sequential access patterns. For the memory-based architecture, the modified cached-memory structure is employed in addition to the techniques used in the pipelined FFT architecture. The hardware implementation results of 2k-point FFT with a 0.11- $\mu {\mathrm{ m}}$ CMOS technology show that the proposed eDRAM-based pipelined and cached-memory FFTs achieve 26.8% and 33.2% power savings over the static RAM-based FFT design, respectively.

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches

In this paper, we propose a reconfigurable (RC) fast Fourier transform (FFT) design in a systematic design scheme. The RC design bricks are mainly proposed to arbitrarily concatenate to support FFT-point required. Meanwhile, we show three developed design techniques, including six-type RC processing element, systematic first-in first-out reuse arrangement, and section-based twiddle factor generator to elaborate our FFT design. In a design/implementation example, it can support up to 2187 FFT-point manipulation and 48 RC modes. It also supports 32 operating modes defined in 3GPP-LTE standard. In application-specified integrated circuit implementation with TSMC 90-nm CMOS technology, our design work occupies a core area of 1.664 mm2 and consumes 35.2 mW under maximal clock frequency of 188.67 MHz. This paper also has outstanding design performance in terms of speed-area ratio and power-frequency ratio for comparison reference.

Implementation of parallel FFT algorithm on a ternary optical computer

The Fast Fourier Transform (FFT) is widely used in modern digital signal processing systems. In order to improve the efficiency of FFT, parallel methods are often used to speed up FFT in high-speed real-time application environments. However, due to the restrictions of size, energy consumption, heat dissipation etc., traditional electronic methods are becoming unsuitable for FFT applications in certain areas, such as aviation, aerospace, etc. Due to its characteristics of a massive number of data bits and low energy consumption, the Ternary Optical Computer (TOC) is a potential solution for these special cases. To verify this possibility, we studied the design and implementation of a high-speed parallel FFT on a TOC. Through analysis of the traditional radix-2, radix-4, and radix-8 DIT FFT operation processes, several FFT algorithms with higher parallelism, implemented on TOC, are designed by taking advantage of the characteristics of TOC. The implementation processes of these algorithms and the differences between them are presented. Meanwhile, the clock cycles and hardware resources required for each algorithm are also discussed. Simulation results reveal that the FFT implementation method is accurate. The algorithms require less power and fewer clock cycles when implemented on a TOC compared to the traditional methods implemented on an FPGA. This provides a new possible solution for high-speed low-power FFT implementation.