Electronic Circuit Design Research Articles

WORKSHOP PENGENALAN PROGRAM DESAIN PCB MENGGUNAKAN PROTEUS DI SMK SAFAATUL UMMAH BREBES

This workshop was held to introduce the Proteus program as a PCB (Printed Circuit Board) design and simulation tool to Safaatul Ummah Brebes Vocational School students, with the main aim of increasing their understanding and skills in designing electronic circuits. This activity includes an introductory theoretical session regarding the basics of using Proteus, a demonstration of making PCB designs, and hands-on practice by participants to complete simple projects. The implementation method consists of a combination of lectures, demonstrations, and project-based practice, with assistance by instructors to ensure participants understand each step. The results of the activity showed that most of the participants succeeded in completing a simple PCB design, showing an increase in their technical abilities. Post-activity evaluation also indicated that this workshop provided significant benefits in broadening students' insight into electronic circuit design and motivating them to learn more about electronic technology. With these positive results, it is hoped that similar activities can be carried out on an ongoing basis to support the development of student competencies in the field of electrical engineering.

SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation

Field-Programmable Gate Array (FPGA) timing simulation is essential in electronic circuit design, allowing for the verification of timing characteristics like delays and clock frequencies. However, bugs in timing simulation tools can lead to inaccurate results, potentially causing designers to miss critical issues in chip performance. Traditional testing methods often fall short in thoroughly assessing these tools, as current FPGA testing primarily focuses on synthesis and behavioral simulation, neglecting timing aspects. To address this issue, we propose SIMTAM for testing timing simulation tools. Specifically, SIMTAM consists of three components: equivalent delay region construction, diversity program segment generation, and differential testing. Given a seed circuit design file written by hardware description language such as Verilog, the delay region construction component randomly identifies delay structures for inertial delay in the design file to construct equivalent delay sleep regions. In the sleep region, the simulator skips the signal pulse whose width is less than the specified delay, thus ensuring the equivalence of the variations. The diversity program segment generation component combines Verilog expressions using generation operators and inject them into the sleep region to generate diverse design files. The differential testing component compares the seed and variant design files to find compilation inconsistency issues. In five months, SIMTAM reported 16 bugs to developers in two popular timing simulation tools Iverilog and Vivado; ten of which are confirmed.

Implementation of Three Phase Induction Motor Pre-Design Program on Electronic Circuit

In this study, the performance analysis of a 5.5 kW, 460 V, 60 Hz, 4-pole, and 3-phase squirrel- cage induction motor (IM) has been carried out by developing a portable electronic circuit, design, and the software, independent of any commercial software. The mathematical equations used in the design steps and the preliminary design of the main dimensions of the squirrel cage IM are realized with a developed electronic circuit. To perform preliminary design calculations Nextion 7-inch touch screen, Arduino mega 2560 microcontroller is used in electronic circuit design. Briefly, IM basic data are entered from the Nextion 7 inches touch screen in the electronic circuit created and the data are sent to the Arduino Mega 2560 microcontroller card via serial communication. On the Arduino Mega 2560 microcontroller board, IM mathematical calculations are accomplished, and the calculation results are presented on the Nextion screen. It has been observed that the analytical calculations and the calculation results in the developed calculation tool have been obtained in good agreement.

Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review

Background: Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits. Objectives: To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters. Findings: It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage. Novelty: The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. Keywords: Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

A Comprehensive Review on Control Technique and Socio-Economic Analysis for Sustainable Dynamic Wireless Charging Applications

Dynamic wireless power transfer (DWPT) has garnered significant attention as a promising technology for electric vehicle (EV) charging, eliminating the need for physical connections between EVs and charging stations. However, the improvement in power transfer efficiency is a major challenge among the research community. Different techniques are investigated in the literature to maximize power transfer efficiency. The investigations include the power electronic circuit, magnetic coupler design, compensating capacitance and control technique. Also, the investigations are carried out based on the type of wireless charging system, which is either a static or dynamic scenario. There are a good number of review articles available on the power electronic circuit and compensator design aspects of WPT. However, studies on the controller design and tracking maximum efficiency are some of the important areas that need to be reviewed. This paper provides a comprehensive review of bibliometric analysis on the DWPT technology, design procedure, and control technique to increase the power transfer and socio-economic acceptance analysis. The manuscript also provides information on the challenges and future direction of research in the field of DWPT technology.

Guest editorial for the special issue on “Artificial intelligence and machine learning based approaches for modeling and design of electronic devices, circuits, and systems”

Guest editorial for the special issue on “Artificial intelligence and machine learning based approaches for modeling and design of electronic devices, circuits, and systems”

A one-dimensional branching rule based branch-and-bound algorithm for minimax linear fractional programming

This paper investigates a type of minimax linear fractional program (MLFP) that often occurs in practical problems such as design of electronic circuits, finance and investment. We first transform the MLFP problem into an equivalent problem (EP) by using the Charnes–Cooper transformation and introducing an auxiliary variable. A linear relaxation strategy should simplify the nonconvex parts of the constraints in (EP). For globally solving MLFP, a branch-and-bound algorithm is then developed. It integrates the presented relaxation with the one-dimensional branching. The convergence of the algorithm is demonstrated and the number of worst-case iterations is estimated. Finally, preliminary numerical experiments verify that the proposed algorithm in this article is robust and efficient for solving the tested instances.

Performance Analysis of Positive Output (P/O) Push-Pull Switched Capacitor Converter for High Power Density Applications

The micro-power-consumption technique requires high power density DC/ DC converters and power supply sources. In this research, a PI and Fuzzy Logic Controllers for an elementary circuit of positive output (P/O) push-pull switched capacitor converter has developed for high power density applications with high sustainability under enormous line and load disturbances. The voltage lift technique is a popular application in electronic circuit design. The power converter performs DC-DC step-up voltage conversion with high efficiency, high power density and cheap topology in a simple structure. The proposed converter combines both switched-capacitor and voltage lift techniques. Referable to the time varying and switching nature of the power electronic converter their dynamic behavior becomes highly nonlinear. Conventional controllers are incapable of providing excellent dynamic performance and hence the fuzzy logic controller can be used as a feed forward controller for controlling power electronic converters. The control algorithm is developed to ensure tracking of the reference voltage and rejection of system disturbances by successive measurements of the converter output voltage at certain time instants within a conduction period. The simulation of PI and Fuzzy logic controls have been carried out using MATLAB/Simulink software to evaluate the controller’s performances. Keywords: Luo converter, DCDC converter, PI Controller, Fuzzy Controller.

DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design

DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design

Optimal placement of multiple finite-size rectangular facilities in an existing layout

ABSTRACT In this paper, we investigate a new problem of optimal placement of multiple finite-size rectangular facilities with known dimensions in the presence of existing rectangular facilities. This problem has applications in facility layout (re)design in manufacturing, distribution systems, services, and electronic circuit design. Three types of facility interactions are considered: between new facilities and existing facilities; between pairs of existing facilities; and between pairs of new facilities. All interactions are serviced through a finite number of input/output points located on the facility boundaries. Travel is assumed to occur according to the rectilinear (or Manhattan) metric and travel through facilities is prohibited. The objective is to find the simultaneous and non-overlapping placement of new facilities, which minimises the total weighted distance (Minisum objective) between the interacting facilities. To arrive at a solution, we divide the feasible region into sub-regions and prove that the candidates for optimal placement of the new facilities can be drawn from the sub-region boundaries. Being a continuous generalisation of the quadratic assignment problem, the solution complexity of this procedure is exponential in the number of new facilities. Our main contribution is the rigorous treatment of an important problem that unifies facility location and layout theories with minisum objective and rectilinear metrics.

Fractional order capacitance behavior due to hysteresis effect of ferroelectric material on GaN HEMT devices

AbstractIn recent years, gallium nitride (GaN) high electron mobility transistors (HEMTs) have come to the forefront of the semiconductor industry because of their exceptional performance in both high‐power and high‐frequency utility. Accurate capacitance modeling is crucial to optimize performance and facilitate energy‐efficient electronic circuit design. In order to reflect the complex nature of the aluminum scandium nitride (AlScN) gate capacitance in GaN HEMTs this study investigates the use of the unique Grünwald‐Letnikov model based on fractional order calculus. The proposed model presents a powerful approach to accurately characterize capacitance since fractional order derivatives allow modeling of non‐integer order systems. Quantitative assessment of the Grünwald‐Letnikov model's accuracy is performed through various error metrics, including mean absolute error (MAE), root mean square error (RMSE), maximum percentage error (MPE), mean absolute percentage error (MAPE), and mean squared error (MSE), by comparing the model's predictions to experimental data. Notably, this model demonstrates remarkable consistency in error metrics, with maximum values of MPE = 0.21%, MAE = 0.05%, MAPE = 0.33%, MSE = 0.01%, and RMSE = 0.09% for the forward scan, and MPE = 0.32%, MAE = 0.04%, MAPE = 0.39%, MSE = 0.01%, and RMSE = 0.08% for the backward scan. These metrics affirm the model's precision in capturing the nuanced capacitance characteristics of GaN HEMT devices. Hence, herein for the first time, the novel Grünwald‐Letnikov model, augmented by fractional order calculus, proves to be a robust tool for accurately characterizing GaN HEMT capacitance. Its ability to seamlessly account for the complexities introduced by using ferroelectric material highlights its potential for advancing semiconductor design and optimizing device performance.

A Review of mm-wave Antenna Design at 60 GHz for 5G Applications System

The rapid advancement of mobile technology is closely tied to developments in electronic circuit designs and computer science. As a result, it is important to monitor the progress of antenna systems, which form the foundation of wireless technology. Microstrip patch antennas have emerged as a leading design in modern communication methods due to their small size, low cost, and ease of manufacturing. Over the past 40 years, numerous studies have been conducted on antenna systems, and this review article provides a comprehensive overview of the earlier and more recent achievements in microstrip patch antennas in the 60 GHz band, which is a crucial frequency range for fifth-generation (5G) technologies. This article discusses mm-wave antennas operating at 60 GHz and provides brief descriptions of their properties, construction techniques, and some related difficulties.

Stability Characterizing Function for Electronic Circuit Design Based on Frequency-Domain Analysis With Parametric Damping

Stability Characterizing Function for Electronic Circuit Design Based on Frequency-Domain Analysis With Parametric Damping

Design of CNTFET-Based Electronic Circuits: A Review

In this review, we present some designs of CNTFET-based circuits, already proposed by us, and critically examine them here. For some of these, we compare the performance of proposed circuits both in CNTFET and CMOS technology. For the CNTFET model, we use a compact, semi-empirical model, already proposed by us and briefly recalled, while, for the MOSFET model, we use the BSIM4 one of the ADS library. Moreover in some design examples, we compare our results with those obtained using the Stanford model. All simulations are carried out using the software advanced design system (ADS), which is compatible with the Verilog-A programming language.

An electrogram-guided transvenous temporary pacemaker implant simulator.

Transvenous temporary pacemaker (TvTP) implantation is a critical procedure often performed under time limitations, playing a crucial role in patient survival. However, the amount of training provided for resident cardiologists is variable, due to the availability of patients. Thus, the use of simulators for this cardiologic procedure could be used as training tools. The present study aimed to develop a simulator system for TvTP implantation based on electrograms, called ETTIS (Electrogram-guided Transvenous Temporary-pacemaker Implantation Simulator), and to evaluate its educational potential and cardiology residents' perceived learning efficacy as a training tool. The development of the ETTIS involved three stages: (1) Adaptation of an anatomical mannequin; (2) Design and manufacture of electronic circuits and software capable of identifying the catheter contact site within the heart chambers and reproducing electrograms in both surfaces (mode-on) and intracavitary (mode-off); (3) To evaluate its educational potential, a modified Likert questionnaire was administered to nine cardiology experts. Additionally, to evaluate the perceived learning efficacy, another modified Likert questionnaire was given to six cardiology residents both before and after training with the ETTIS. Descriptive statistics with measures of position and dispersion were employed, and the weighted Kappa test was used for agreement analysis. A high rate of acceptance (over 90%) was found among experts who evaluated the ETTIS. The cardiology residents showed significant self-perceived learning gains, as evidenced by a lack of agreement between their responses to a questionnaire before and after training. The ETTIS is a promising tool for medical training, displaying both educational potential and efficacy. It has been shown to be effective in learning a variety of skills, including cardiac catheterization and electrophysiology. Additionally, the ETTIS is highly engaging and allows cardiology residents to practice in a safe and controlled environment.

A Modeling Approach for Designing New Acoustic Materials

In this study, mathematical modeling design based on Sound Transmission Loss measurement results of new acoustic material samples with natural content was carried out. Using the test samples in question, transfer function of acoustic materials based on electronic filter circuit design and a transition design method for the production of new acoustic materials by utilizing the transfer function is presented. Based on the experimental results of the test samples, it is the most suitable low-pass filter structure for the proposed design. In this study, active Sallen-Key low-pass filter structure is preferred and used. Sound Transmission Losses in dB (decibels) of acoustic samples were obtained experimentally for 500, 1000, 2000 and 4000 Hz. fundamental frequencies in the literature. Based on these data, transfer function simulation suppression gain results were obtained in TINA-TI program, active filter circuit designed, and MATLAB program. When the other results were compared in the experimental results, it was seen that very close values were obtained. It has been demonstrated that the proposed method can be used effectively in the design and examination of new acoustic materials.

A microfluidic transistor for automatic control of liquids

Microfluidics have enabled notable advances in molecular biology1,2, synthetic chemistry3,4, diagnostics5,6 and tissue engineering7. However, there has long been a critical need in the field to manipulate fluids and suspended matter with the precision, modularity and scalability of electronic circuits8–10. Just as the electronic transistor enabled unprecedented advances in the automatic control of electricity on an electronic chip, a microfluidic analogue to the transistor could enable improvements in the automatic control of reagents, droplets and single cells on a microfluidic chip. Previous works on creating a microfluidic analogue to the electronic transistor11–13 did not replicate the transistor’s saturation behaviour, and could not achieve proportional amplification14, which is fundamental to modern circuit design15. Here we exploit the fluidic phenomenon of flow limitation16 to develop a microfluidic element capable of proportional amplification with flow–pressure characteristics completely analogous to the current–voltage characteristics of the electronic transistor. We then use this microfluidic transistor to directly translate fundamental electronic circuits into the fluidic domain, including the amplifier, regulator, level shifter, logic gate and latch. We also combine these building blocks to create more complex fluidic controllers, such as timers and clocks. Finally, we demonstrate a particle dispenser circuit that senses single suspended particles, performs signal processing and accordingly controls the movement of each particle in a deterministic fashion without electronics. By leveraging the vast repertoire of electronic circuit design, microfluidic-transistor-based circuits enable fluidic automatic controllers to manipulate liquids and single suspended particles for lab-on-a-chip platforms.

Importance of low power electronic circuit design and its impact on energy consumption

<p class="MDPI16affiliation">In the modern world, Integrated Circuits (ICs) are an essential component of any electronic device, and it is practically impossible to imagine a world without them. When addressing energy consumption or environmental issues, many people, including researchers, tend to focus solely on power plants. However, today, there are billions of electronic devices, each containing numerous ICs, such as mobile phones, tablets, televisions, laptops, refrigerators, vacuum cleaners, cars, and more. In other words, a large portion of our modern energy consumption is attributed to electronic devices. Thus, reducing power consumption in each of these devices could significantly impact global energy consumption and environmental pollution. This paper emphasizes the importance of low-power Integrated Circuits and their potential to reduce worldwide energy consumption. It also briefly explores relevant technologies that contribute to energy efficiency in circuits, avoiding unnecessary complexities.</p>

Design and Implementation of Self-Limiting Two-Stage LC Oscillators Using Cascade Structure of Monolithic CCIIs as Active Elements

This paper presents the structure and principle of operation of two circuit configurations of self-limiting LC oscillators using monolithic positive second-generation current conveyors (CCII+s), that are implemented using Current-Feedback Operational Amplifiers (CFOAs) with an available compensation pin (Z). The proposed LC oscillators are synthesized using a systematic approach in the design of analog electronic circuits and can be considered as variants of the basic three-point oscillators, implemented using transistors (BJTs or FETs). Based on the analysis of the structure and electrical parameters of the CFOAs with a compensation pin (Z), electronic circuits of oscillators with two-stage amplifier blocks are synthesized. The characteristic equations and self-oscillation conditions are derived for the obtained analog circuits, and recommendations for designing circuits with arbitrary frequencies are defined. To verify the efficiency of the proposed LC oscillators, an experimental study is performed in the frequency range from 100 kHz to 10 MHz. The CFOAs AD844A with an external terminal z of the internal current conveyor are used as active elements. The obtained experimental results well match the results of the simulation modelling and the parameters based on the derived analytical expressions. The developed LC oscillators are intended to be used in schematic configurations of gas sensors based on surface acoustic wave (SAW) resonators.

Variation Aware Optimization vs Classical Margin Optimization of Superconducting Electronics

We have developed a Superconducting Electronics Circuit Design Optimizer in conjunction with a Statistical Process Variation Josephson Junction Model and formal method of Logic Verification as a means to optimize circuits and mitigate their susceptibility to factors of yield loss. In this paper we will contrast the Yield improvement provided by direct yield optimization against classical methods of margin centering.