Design Of Down-conversion Mixer Research Articles

Wideband ring mixer for band #1 of MB-OFDM systems in 180 nm CMOS technology

Abstract A wideband down conversion ring mixer is proposed for multi band orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm CMOS technology. The mixer is essentially used in a heterodyne wireless receiver to enhance the selectivity of the system. Being a nonlinear system, the mixer dominates the overall performance of the system. The design of down conversion mixer is the most challenging part of a receive chain. Wideband impedance matching always remains a challenge in any radio frequency integrated circuit design. This paper presents the design of a ring mixer with high linearity, wideband impedance matching using differential resistive impedance matching and without using any DC bias. The proposed mixer is tuned for a frequency of 3.432 GHz of band 1 of the MB-OFDM system. Mixer core is based on the FET ring mixer topology. The mixer is implemented in 180 nm CMOS technology. The mixer achieves the minimum conversion loss of 10.49 dB, 1 dB compression point (P1) of 12.40 dBm, third order input intercept point (IIP3) of 12.01 dBm, a minimum SSB noise figure of 8.99 dB, and S 11 of less than -10 dB over the frequency range of 0 to 13.61 GHz . The layout of the mixer records an active area of 183.75 μm 2 .

Compact Down-Conversion Mixer Design Employing a Wide and Deep Stop-Band DGS-LPF

Compact Down-Conversion Mixer Design Employing a Wide and Deep Stop-Band DGS-LPF

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13μm CMOS technology. Dissipating 0.26mW from a 1.2V supply, the fabricated PLL can track signals between 1.62 and 2.49GHz. For receiver applications, the energy per bit of the receiver is only 0.26nJ making it attractive for low power applications including wireless sensor networks.

CMOS RF Down-Conversion Mixer Design for Low-Power Wireless Communications

This paper aims to study the design of a low-power single-balanced mixer for downconversion in wireless RF receivers. The proposed circuit is designed to work at a radiofrequency of 1.9GHz using CMOS 0.18 µm technology. The obtained results show a conversion gain equal to 7 dB and low power consumption of 3.86mW at 1.8.V supply voltage. The single side band noise figure performance was founded to be 8.dB. These results show a good potential of this CMOS mixer and justify its use for low-power wireless communications.

CMOS RF Down-Conversion Mixer Design for Low-Power Wireless Communications

This paper aims to study the design of a low-power single-balanced mixer for downconversion in wireless RF receivers. The proposed circuit is designed to work at a radiofrequency of 1.9GHz using CMOS 0.18 µm technology. The obtained results show a conversion gain equal to 7 dB and low power consumption of 3.86mW at 1.8.V supply voltage. The single side band noise figure performance was founded to be 8.dB. These results show a good potential of this CMOS mixer and justify its use for low-power wireless communications.