CMOS Design Research Articles

Design and performance investigation of tunnel-FET based energy efficient approximate and accurate adders targeted towards low power IoT nodes

Abstract The proliferation of IoT enabled SoCs in state-of-the-art consumer electronics has necessitated the use of beyond CMOS devices for the energy efficient computations and sensing design space. In the low supply voltage (VDD) regime, Tunnel FETs (TFETs) have shown serious potential at VDD less than 0.5 V. However, the inherent structure, characteristic interband tunneling and enhance Miller capacitance in TFETs do not allow the conventional CMOS logic design styles to be universally used for TFET based logic circuits. In this paper, we propose three energy efficient and novel TFET based accurate adder circuits namely, Static Energy Recovery Full adder (SERF), Complementary and Level Restoring Carry Logic Full adder (CLRCL) and Balanced Restoring Carry Logic full adder (BRCL) based on constituent TFET based functional units which do not use the CMOS design style. Further, novel approximate adders have been developed for energy efficient implementation in IoT nodes. The BRCL adder consumes approximately 60% less area and 85.36% and 89.6% less energy in comparison to SERF and CLRCL respectively. The approximate adders in the best and worst case facilitate approximately 92% and 75% savings in area and consumes 71% less power than the BRCL adder. When compared to the standard UMC 45 nm bulk MOSFET based designs, the TFET based accurate adders operate at 25% less energy while the approximate adders consume 40% less. All the circuit simulations have been performed using Spectre Simulator of Cadence and device characterization using 2D-TCAD tool.

MicroLED arrays—A perspective beyond displays

MicroLEDs, particularly when integrated with CMOS microelectronics, represent a significant advancement in nitride technology. While large-area, high-power LEDs for solid-state lighting have seen extensive optimization, microLEDs present unique fabrication and characterization challenges. Utilizing standard CMOS design and foundry services for silicon driver electronics, a new hybrid interconnect technology must be developed for chip–chip or wafer–wafer integration, necessitating much higher lateral resolution than current bonding technologies. Beyond display technology, microLED integration opens avenues for groundbreaking applications such as highly efficient nanosensors, miniaturized optical neuromorphic networks, and robust chip-based microscopy. This paper explores recent advancements in nitride/CMOS hybrid modules, providing an overview of current technologies and future possibilities in this dynamic field.

Design of CMOS Based LC-Voltage Control Oscillator Using Substrate Bias Effect and Current Mirror Technique

Design of CMOS Based LC-Voltage Control Oscillator Using Substrate Bias Effect and Current Mirror Technique

Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications

Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency

A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs.

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a negative capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40 nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, T fe of 3 nm, the energy consumption of the proposed accurate NCFET based CiM design is ∼82.48% lower in comparison to the conventional/Non CiM full adder design and ∼85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at V DD = 0.5 V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ∼4.19x lower energy consumption and ∼4.47x lower energy consumption in approximation mode when compared to the baseline 40 nm CMOS design at V DD = 0.5 V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters

This manuscript shows the CMOS design of Lorenz systems using operational transconductance amplifiers (OTAs). Two Lorenz systems are then synchronized in a master–slave topology and used to implement a CMOS secure communication system. The contribution is devoted to the correct design of first- and second-order OTA-C filters, using 180 nm CMOS technology, to guarantee chaotic behavior. First, Simulink is used to simulate a secure communication system using two Lorenz systems connected in a master–slave topology, which is tested using sinusoidal signals that are masked by chaotic signals. Second, the Lorenz systems are scaled to have amplitudes of the state variables below 1 Volt, to allow for CMOS design using OTA-C filters. The transconductances of the OTAs are tuned to accomplish a Laplace transfer function. In this manner, this work highlights the design of a second-order CMOS OTA-C filter, whose damping factor is tuned to generate appropriate chaotic behavior. Finally, chaotic masking is performed by designing a whole CMOS secure communication system by using OTA-C based Lorenz systems, and its SPICE simulation results show its appropriateness for hardware security applications.

Design and Implementation of CMOS and Transmission Gate Based Full Adder Using 45nm Technology

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied, and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Transmission gate based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Transmission gate based Full adder circuits. The entire circuit is simulated in Cadence Tools at 45nm CMOS process.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Design and optimization of CMOS based 4-bit comparator

The paper primarily focuses on optimizing circuit delay and energy consumption, specifically in gate-level circuits. Three methods are employed for circuit optimization. The first method aims to minimize transistor usage to reduce both delay and energy consumption. The second method involves prioritizing logic gates based on underlying hardware, favoring simpler circuit structures whenever possible, given that our design primarily revolves around logic gates. The third method entails adjusting the number of stages to enhance delay optimization. To validate these rules, three distinct circuits were designed to implement a 4-bit absolute value comparator, each corresponding to one of the rules. Through simulation, calculation, and comparison, the best circuit was identified, providing validation for the rules. The second part of the paper shifts its focus towards optimizing delay and energy consumption by adjusting the sizing of logic gates and the supply voltage to achieve optimal overall performance. In conclusion, further research is needed to corroborate these three rules and identify additional rules, laying the foundation for intelligent circuit optimization.

Active matrix-based pressure sensor system with a 4 × 16 printed decoder designed with a flexible hybrid organic process design kit

The innovative field of printed sensor with a demand for high accuracy, sensitivity and durability has enabled a wide application area in sensing, healthcare etc. A large-area printed sensor system on a flexible foil substrate emplying p-type organic field-effect transistors (OFETs) is presented. Thereby, the OFET is fabricated through a hybrid manufacturing process, including photolithographically structured source- and drain-electrodes, ink-jet printed organic semiconductor, and spin-coated dielectric. Moreover, a dedicated device model, derived from the variable range hopping model, is developed and integrated together with process related design rules, materials properties and geometric information into a comprehensive process design kit (FH_OPDK). The FH_OPDK is integrated in a commercial electronic design automation tool and is used to design and perform post-layout simulations on logic gates, such as INV, NAND2, and NOR2 as well as circuitry such as ring oscillators and a 4 × 16 digital decoder. Several circuit topologies have been tested and evaluated in a detailed model-hardware correlation analysis. Finally we have optimized logic gates and the decoder in a PMOS only, pseudo CMOS design style. To demonstrate the feasibility of the full sensor system in hardware a 16 × 16 active matrix pressure sensor on a flexible substrate integrated with a 4 × 16 binary decoder was fabricated and tested. We have integrated our flexible hybrid sensor system with a PCB board and a microcontroller to demonstrate the hardware readout platform capable of detecting the weight of objects and visualizing a digital map of applied forces.

Analog CMOS Design in Nanometer Regime

There is no doubt that the short-channel effects have affected the analysis and design of modern analog CMOS integrated circuits significantly. Thus, models that take into account these effects must be adopted in order to obtain more accurate results. In this paper, the AC small-signal low-frequency equivalent circuit of the short-channel MOSFET transistor is developed using an appropriate model. The impact of short-channel effects on the operation of basic building blocks of analog integrated circuits such as basic amplifier configurations, cascode stage, differential amplifier and composite transistor is investigated quantitatively. Additionally, the nonlinear distortion is investigated using the adopted model.

Design of K-Band CMOS Extended Cascode Power Amplifier With Second Harmonic Termination to Enhance Output Power

Design of K-Band CMOS Extended Cascode Power Amplifier With Second Harmonic Termination to Enhance Output Power

Design of CMOS Integrated Circulator Based On Sequentially Switched Delay Lines With Body-Floating and Clock Boosting Techniques

Design of CMOS Integrated Circulator Based On Sequentially Switched Delay Lines With Body-Floating and Clock Boosting Techniques

A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions [Feature

Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions [Feature

Design and analysis of high-resolution CMOS digitally controlled oscillator with tunable transformer

A tunable transformer based millimeter-wave digitally controlled oscillator (DCO) is proposed to achieve high frequency resolution with compact area in this paper. An 8-shaped inductor is employed as primary coil of the transformer to generate the opposite magnetic field and achieve a weak coupling to the secondary coil, which is beneficial to enhance the scaling effect of the capacitor to achieve a smaller equivalent capacitance. The equivalent model of the transformer structure is analyzed theoretically. Distributed capacitors are placed under the secondary coil, which can be flexibly adjusted to achieve high frequency resolution. A digitally controlled artificial dielectric (DiCAD) differential transmission line is implemented to achieve coarse and medium frequency tuning. The DCO is implemented in 40-nm CMOS process with a core area of 0.026 mm2. Simulated results demonstrate a minimum frequency tuning step of 381 KHz with a frequency tuning range of 12.3% from 58.60 to 66.28 GHz, and the phase noise at 1-MHz offset is from −91.3 to −94.0 dBc/Hz, corresponding to an FoM range of −179.5 to −182.2 dB, while the power consumption is 8.8 mW.

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits