Design Of CMOS Operational Amplifier Research Articles

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

This paper provides a detailed exploration of CMOS operational amplifiers (Op-Amps) aimed at enhancing understanding of their development, design, and application. To achieve this, a comprehensive examination of the common characteristics, parameters, and bibliographic reviews of Op-Amps, distinguishing among various chosen operational amplifiers. A comprehensive bibliographic review of the operational amplifier's keywords between 2008 and 2018 has also been conducted. A bibliometric analysis of 4997 documents from the Web of Science (WOS) Collection is conducted using VOSviewer software. Furthermore, an analysis and comparison of these Op-Amps across functional aspects relevant to industrial and biomedical applications, emphasising the salient characteristics of each technique. After the survey, a novel Op-Amp design is proposed, incorporating a differential amplifier at the first stage, along with a compensating capacitor and a high gain stage. The biasing circuitry is replaced with an active load resistor (MOS transistor), simplifying layout design, and reducing the amplifier's area and power consumption compared to traditional two-stage designs. The power source for this design is 3.3 V. This designed operational amplifier achieved a gain of 62.9449 dB, a high CMRR of 92.8079 dB, and a unity gain bandwidth of 33 MHz, and the optimised layout area is 0.001476 μm2. The proposed circuit was designed and simulated utilising the Cadence Virtuoso 180 nm CMOS process. The simulation results show that the desired criteria have been met. Additionally, the challenges and future possibilities in analog circuits, laying the groundwork for research in both analogue and digital circuits to tackle complex real-world issues have been addressed.

A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry

This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.

On the Operation of CMOS Active-Cascode Gain Stage

An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.

Low‐voltage rail‐to‐rail CMOS operational amplifier design

AbstractThis paper describes the design of a low‐voltage CMOS rail‐to‐rail operational amplifier. We have designed input signal compression circuitry that compresses rail‐to‐rail input signals to the input range of the following folded‐cascode operational amplifier, which is capable of rail‐to‐rail output. The input signal compression circuitry and the following folded‐cascode operational amplifier together comprise an input‐output rail‐to‐rail operational amplifier. SPICE simulation with 0.18−µm CMOS BSIM3v3 parameters validates the operation of the rail‐to‐rail CMOS amplifier with supply voltage of 0.7 V and bias current of 3.1 µA. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(12): 1–7, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20297

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-/spl mu/m CMOS process. Experimental results are provided and the corresponding performances are discussed and compared.

Novel CMOS operational amplifier design technique for high-frequency switched-capacitor applications

The paper presents a design technique that enhances the operational characteristics of CMOS operational amplifiers for high-frequency switched-capacitor applications. The design approach introduces a method of settling time reduction that uses predefined layout blocks that can be placed side by side to perform the desired topological scaling for minimum settling time against load capacitance. Further, the method lends itself well with the current CAE tools available which perform cell placement and interconnect routing. This technique allows a designer to quickly implement an operational amplifier that is optimised in an AC sense for a required load capacitance. Simulation results are presented that demonstrate a possible enhancement in performance of up to 400%.

Analog CMOS integrated circuit design: research and undergraduate teaching

The authors describe the use of software that was developed as part of a research program in analog CMOS integrated circuit design for an undergraduate course on analog VLSI design. The software includes some unusual uses of readily available, inexpensive, and easy-to-use programs available for microcomputers such as Macintosh or IBM-PC clones. Although initially intended to help with the design of CMOS operational amplifiers, the IC design method used is very general; other possible applications are described. The flexibility of these programs also allows them to be used with other CAD (computer-aided design) software, including circuit simulators and programs for schematic entry and layout. The software tools allow undergraduate students to complete analog CMOS integrated circuit designs using advanced CAD techniques but without being overwhelmed or losing touch with the underlying circuit design principles. Details of the programs and their use are presented together with the resulting analog IC designs fabricated using MOSIS (MOS Implementation Service). >