Abstract

An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.

Highlights

  • Invented in 1979 [1] and subsequently refined in 1990 [2,3,4], the CMOS active-cascode gain-enhancement technique1 finds wide applications in analog integrated circuits, such as Nyquist-rate and oversampling data converters, sample-and-hold amplifiers, switched-capacitor filters, band-gap reference circuits, and voltage regulators

  • In an attempt to achieve a high unity-gain frequency and a high dc gain simultaneously, the active cascode introduces a pole-zero pair near the unity-gain frequency of the auxiliary amplifier, which potentially leads to slow-settling behavior of such op amps [2]

  • This paper examines the doublet behavior of CMOS active cascodes

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Summary

Introduction

Invented in 1979 [1] and subsequently refined in 1990 [2,3,4], the CMOS active-cascode gain-enhancement technique finds wide applications in analog integrated circuits, such as Nyquist-rate and oversampling data converters, sample-and-hold amplifiers, switched-capacitor filters, band-gap reference circuits, and voltage regulators. By boosting the low-frequency transconductance of the cascode device, the technique increases the output resistance of a CMOS cascode operational amplifier (op amp), and the voltage gain without degrading its high-frequency performance. As a result, it is ideally suitable for on-chip applications, where a large gainbandwidth product is desirable while driving capacitive loads.

CMOS Cascode Gain Stage
Small-Signal DC Gain
Frequency Response
Output Resistance and Gain
Frequency Doublet
Slow Settling
Solving Doublet
Open-Loop Transfer Function
Closed-Loop Settling Behavior
Computer Simulation
Intrinsic Doublet Behavior
Effect of Other Parasitics
Effect of the Second Pole
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