Analog Front-end Design Research Articles

A Low-Cost Data Acquisition System Design for Multifunctional Test Equipment in Electronics Laboratories

There are various commercially available multifunctional electronics laboratory test equipment on the market that integrates an oscilloscope, signal generator, and logic analyzer. The price point for all these devices typically exceeds USD 250. To lower this cost to around USD 100, the data acquisition components of these devices need to be re-evaluated. In this paper, we present the design of an analog front-end (AFE) for low-cost multifunctional laboratory equipment, mainly for electronics students. The primary objective was to meet student requirements while ensuring minimal cost, maximum functionality, and high robustness. Through our research, we optimized our AFE design to achieve these objectives effectively. Our approach addresses key limitations found in existing designs, as we developed four-stage attenuation and three-stage op-amp gain architecture. This arrangement optimizes signal clarity and achieves high bandwidth while maintaining a cost-effective framework suitable for educational applications. With this study, a 20 MHz bandwidth, ±40 V input voltage range, volt/div range from 5 mV to 10 V, and minimum amplitude resolution of 9.7 µV were achieved in the design of the analog front-end and data acquisition unit. The achieved bandwidth and linearity enable designed AFE to accommodate applications such as ultrasonic discrete TGC (Time Gain Compensation).

A 0.064 mm2 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 μm × 65 μm compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 μVrms. Power consumption is also tested, with a measured value of 3.77 μW per channel, corresponding to an overall consumption of about 60 μW. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results.

Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

This paper provides an assessment of the electrical and noise performance in the 180 nm double silicon-on-insulator (DSOI) technology, which shows advantages for analog front-end radiation detectors. For the first time, the impact of the back-gate voltage on the electrical and noise performance of DSOI MOSFETs is investigated. The transconductance-to-current (gm /ID ) ratio and low-frequency (1/f) noise were measured as a function of the MOS device types (NMOS/PMOS), gate length, and bias condition of front- and back-gates. Experimental results show that positive back-gate voltage deteriorates the gm /ID ratio of the MOSFETs in weak inversion region. The DSOI NMOS devices overwhelm the PMOS with better gm /ID and 1/f performance. The DSOI devices have a comparable 1/f noise with the 180 nm SOI counterparts. With negative back-gate voltage applied, the low frequency noise performance of NMOS is improved. This assessment of DSOI technology gives a guideline for the readout circuit design in detector front-end systems.

An ultrahigh input impedance low noise analog front‐end design for epilepsy brain recording system

SummaryThis paper presents an ultrahigh input impedance, low noise, and wide bandwidth four‐channels analog front‐end (AFE) for low‐power neural recording systems. To achieve high input impedance, the buffer channels are placed between the electrodes and the main amplifier stage of the AFE. The buffer is designed with low noise and low power consumption to obtain high input impedance of overall AFE while maintaining low input‐referred noise and low power consumption. A chopper capacitively coupled chopper instrumentation amplifier (CCIA) is placed after the buffer as the main amplifier stage of the AFE to improve the common mode rejection ratio (CMRR) and the input‐referred noise of the overall AFE design. A new chopper stabilization control technique is proposed and used in the CCIA stage to reduce the charge injection and clock feedthrough and consequently the high‐frequency ripple of the AFE output signal. A programmable gain amplifier (PGA) is designed as the third stage to adjust the overall gain of the AFE. Benefiting from PGA, the AFE can adapt its gain with both action potential and local field potential signals. To reduce the number of the electrode to be implanted and reduce the impedance mismatch that causes the degradation on overall CMRR performance, two AFE channels shared a reference electrode followed by a reference buffer. The proposed AFE is designed and simulated using a standard 180 nm CMOS process and operates in a wide frequency band of 2.1 to 2500 Hz with low input‐referred noise of 1.6 μVrms and a CMRR over 80 dB at 2.1 Hz. The total power consumption is lower than 4.3 μW per channel. With the proposed structure of AFE, the input impedance is 35 GΩ @ 21 Hz and the minimum impedance over operational bandwidth is 75 MΩ @ 2.5 kHz.

IoT Device for Long-Term ECG Monitoring in Collaborative Environment

Ubiquitous electrocardiography (ECG) sensing with wireless connectivity will be a solid alternative to conventional in-hospital healthcare surveillance. This paper presents a prototype for long-term ECG measurement equipment using an IoT environment over a collaborative diagnosis network. We propose a collaborative vision of working on two major paths for designing a device for long-term ECG surveillance: the design path and the decision path. The design path is made from the sensors design, the analog front-end design, the IoT equipment design, the gateway application, to the cloud application. The decision path is from the acquired ECG signal through the software decision at the IoT equipment level and software decision on the gateway level and cloud application level to the highest level represented by the human. We summarized the evolution and performance of Electric Conductive Textiles (ECT) as the primary material for long-term wearable ECG electrodes based on the skinelectrode contact impedance, motion artifacts, signal quality, and skin-electrode chemical interaction. The presented system topology was designed for lower power consumption in a collaborative diagnosis network environment.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

Design of analog front-end integrated circuit of tactile sensor for human-machine interface

—In this paper, a highly integrated analog front-end chip for sensor data acquisition and readout is designed, which is applied to a pressure-to-capacitance-conversion 16 × 16 tactile sensor array. In this design, a 16-channel capacitance-to-digital converter using a combination of op-amp-based Capacitance-Voltage Converter (CVC) and column-parallel Single-Slope Analog-to-Digital Converter (SS ADC) converters has been implemented, increasing the readout speed of the sensor array and saving the chip area. In addition, a sequence of scanning circuit suitable for the 16 × 16 array is proposed, so that the CVC and column-parallel SS ADCs are in a pipelined working mode, which further improves the speed of data conversion and readout. The integrated circuit (IC) is designed and taped out in a 0.18-μm CMOS process technology. The measurement results show that the chip can reach the capacitance detection range from 1 pF to 9.1 pF, and it achieves a detection accuracy of 9 fF under 10-bit ADC quantization. Under the clock frequency of 64 MHz, the refresh rate of the entire array is 3906 fps, and the overall power consumption of the front-end IC is 7.5 mW.

Design of a Low-Power Ground-Free Analog Front End for ECG Acquisition.

This article presents the design of a low-power ground-free (two-electrode) analog front end (AFE) for ECG acquisition. At the heart of the design is the low-power common-mode interference (CMI) suppression circuit (CMI-SC) to help minimize the common-mode input swing and prevent turning on the ESD diodes at the input of the AFE. Fabricated in a 0.18- μm CMOS process with an active area of 0.8 [Formula: see text], the two-electrode AFE can tolerate CMI of up to 12 [Formula: see text], while consuming only 6.55 μW of power from a 1.2-V supply and exhibiting 1.67 μVrms of input-referred noise in a 1-100 Hz bandwidth. Compared to existing works, the proposed two-electrode AFE thus provides a 3× reduction in power for comparable noise and CMI suppression performances.

An ultra-low power dissipation CMOS temperature sensor with an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C

An ultra-low power, high accuracy BJT-based CMOS temperature sensor is presented in this paper. The temperature sensor consists of analog front end (AFE) and hybrid ADC. In AFE design, two dynamic element matching (DEM) control modules are applied to current mirrors and bipolar transistors reduce the mismatch greatly and enhance the sensitivity of the temperature sensor. A hybrid ADC that combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce the power dissipation. The proposed sensor is fabricated in a 0.18 μm CMOS process, occupying an area of 0.14 mm2. The measured results indicate that, the total current is 6.5 μA from a 1.8 V power supply, and achieves an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C.

Characterization of Imaging System for Satellite-Borne Polarization Camera Based on Scientific Grade CCD

The cloud and aerosol polarization camera (CAPC) is an ultrawide angle satellite-borne polarization sensor, which adopts a scientific-grade array charge-coupled device (CCD) with the feature of smearing effect. To realize shorter exposure time and increase the dynamic range for the CCD imaging box of CAPC, the idea of charge dumping is introduced into the CCD timing driving design. Then, the design of power supply, driving timing, and analog front-end (AFE) is studied in detail. Finally, the comprehensive performance of the CCD imaging box is compared by utilizing the large aperture integrating sphere light source. The measurement results indicate that the exposure time of CCD is controlled between 5 and 80 ms, and the linearity error of CAPC at various bands is lower than 0.5%. Under the condition of 90% saturation exposure, the signal-to-noise ratio (SNR) of CAPC is 52.63 dB. The CCD dynamic range can achieve 62.91 dB. The experimental results meet the working requirements of the CAPC and verify the effectiveness of the CCD imaging design.

Simulation of charge sharing effects in 70 μm pixelated CdTe sensor

Pixel detectors become an integral part of medical imaging, nondestructive testing, space science and particle physics. Sensors that are bump bonded to readout ASICs are made from various materials such as GaAs, Si, CdTe, and CdZnTe. Current research tends to use CdTe/CdZnTe as gamma-ray sensors due to its high absorption coefficient in the gamma spectrum. With decreasing size of pixel pitch, charge diffusion and secondary fluorescent photons cause charge sharing between neighboring pixels. That decreases the spatial and spectral resolution of the detector. This study simulated the effects of charge diffusion in a 2 mm thick 70 μm pixelated CdTe using TCAD. We created a 3D model of the sensor with an array of 5 × 5 pixels. We simulated the propagation of e-h pairs generated upon the absorption of gamma photons in CdTe. Based on the simulation outcome, we calculated the collection time, drift time and pixel capacitance. Finally, we propose a sensor model for use in analog front-end design.

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail.The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ∼36mV/ke- when configured in High Gain Mode, and ∼20mV/ke- when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ∼68e-rms and ∼80e-rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ∼ 200ps time bin and the chip can deal with a maximum flux of ∼ 3.6MHzmm−2s−1. In photon counting mode, the chip can deal with up to ∼ 5GHzmm−2s−1.The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

A Design of Analog Front-End with DBPSK Demodulator for Magnetic Field Wireless Network Sensors

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 , 0.063 , 0.045 , and 0.03 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.

A 186μW Photoplethysmography-Based Noninvasive Glucose Sensing SoC

Recent trends in research and the market show high demand for frequent monitoring of glucose to estimate the blood sugar level non-invasively which can replace the conventional finger-prick glucometer for daily use. This paper presents a high precision near-infrared Photoplethysmography (PPG) based noninvasive glucose monitoring System on Chip (SoC). The proposed system implements a fully differential Analog Frontend (AFE) with nonlinear medium Gaussian support-vector-regression (NMG-SVR) for glucose estimation. The AFE design incorporates chopping which enables the reduction of the integrated input-referred current noise to 9.4pArms thus achieving a dynamic range of 115dB. The glucose prediction processor (GPP) removes noise from the PPG signal, extracts ten unique features, and estimates the blood glucose level using a trained customized NMG-SVR model that minimizes the hardware cost by 25%. The extracted features are carefully designed and implemented to ensure inter-feature dependency, which helps to reduce the overall area by more than 40%. Moreover, GPP is implemented using power and clock gating techniques to minimize both static and dynamic power consumption. The proposed SoC is realized with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an area of 6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It dissipates a power of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$186~\mu \text{W}$ </tex-math></inline-formula> and achieves a mean absolute relative difference (mARD) of 6.9% verified on 200 subjects.

Echo Signal Receiving and Data Conversion Integrated Circuits for Portable High-Frequency Ultrasonic Imaging System.

Ultrasonic imaging has become a very promising technology, and it has been widely applied in biomedicine, geology, and other fields due to its advantages of safety, nondamaging, and real time. Especially, the portable high-frequency (>20 MHz) ultrasonic imaging system (UIS) has been generally used in biomedical detection and diagnosis. In the complex actual environment, the effect of integrated circuits (ICs) on the performance of portable high-frequency UIS is obvious. In the echo signal transmission link, the analog front end (AFE) and the analog-to-digital converter (ADC) are the two most critical modules, where AFE is used to receive and preprocess the analog ultrasonic echo signals and ADC to convert the analog signals from the AFE output to digital. The structure and performance of the ICs integrated into terminal equipment and in-probe for the portable high-frequency UIS are introduced and discussed. Some typical commercial ICs are also summarized. Based on the requirements and challenges of portable high-frequency UIS, the future development directions of ICs mainly include high integration, ultralow power consumption, high speed, and high precision, which can provide valuable reference and advice for the design of AFE and ADC for portable high-frequency UIS.

A low-noise analog frontend design for the Taiji phasemeter prototype.

The Taiji program plans to utilize the laser interferometer to measure the movement at the picometer level between free-floating test masses. As the phase readout equipment, the phasemeter needs to obtain the beat note with an accuracy of μrad/Hz. The main source of noise in the phasemeter is the analog frontend of the analog to digital converter. A self-designed phasemeter prototype with a low-noise analog frontend, which includes the theme of the pilot tone correction, has been developed and tested for the Taiji program in this Note. The experimental results show that the performance of the developed phasemeter can satisfy the Taiji sensitivity requirement in the whole frequency range. The sensitivity of the board can reach 0.5 μrad/Hz in the frequency range of 0.1-1Hz. Therefore, the prototype gives us a good model for the fully functional Taiji phasemeter.

A Versatile Analog Electronic Interface for Piezoelectric Sensors Used for Impacts Detection and Positioning in Structural Health Monitoring (SHM) Systems

Continuous monitoring of mechanical impacts is one of the goals of modern SHM systems using a sensor network installed on a structure. For the evaluation of the impact position, there are generally applied triangulation techniques based on the estimation of the differential time of arrival (DToA). The signals generated by impacts are multimodal, dispersive Lamb waves propagating in the plate-like structure. Symmetrical S0 and antisymmetrical A0 Lamb waves are both generated by impact events with different velocities and energies. The discrimination of these two modes is an advantage for impact positioning and characterization. The faster S0 is less influenced by multiple path signal overlapping and is also less dispersive, but its amplitude is generally 40–80 dB lower than the amplitude of the A0 mode. The latter has an amplitude related to the impact energy, while S0 amplitude is related to the impact velocity and has higher frequency spectral content. For these reasons, the analog front-end (AFE) design is crucial to preserve the information of the impact event, and at the same time, the overall signal chain must be optimized. Large dynamic range ADCs with high resolution (at least 12-bit) are generally required for processing these signals to retrieve the DToA information found in the full signal spectrum, typically from 20 kHz to 500 kHz. A solution explored in this work is the design of a versatile analog front-end capable of matching the different types of piezoelectric sensors used for impact monitoring (piezoceramic, piezocomposite or piezopolymer) in a sensor node. The analog front-end interface has a programmable attenuator and three selectable configurations with different gain and bandwidth to optimize the signal-to-noise ratio and distortion of the selected Lamb wave mode. This interface is realized as a module compatible with the I/O of a 16 channels real-time electronic system for SHM previously developed by the authors. High-frequency components up to 270 kHz and lower-frequency components of the received signals are separated by different channels and generate high signal-to-noise ratio signals that can be easily treated by digital signal processing using a single central unit board with ADC and FPGA.

Digital Iterative Harmonic Rejection and Image Cancellation for LPF-Less Frequency-Interleaved Analog-to-Digital Converters

The frequency-interleaved analog-to-digital converter features large bandwidth, high speed, medium-to-high resolution with respectable jitter robustness, albeit suffering from circuit impairments such as spectral leakages, harmonic interferences, in-phase/quadrature and aliasing images. For the first time, a digital compensation framework is introduced to minimize these impacts simultaneously. In this framework, channel recombination is performed before calibration. It circumvents the needs for analog harmonic rejection and channel separation, thus enabling significant simplification of the complex analog frontend design. A comprehensive system model that incorporates all the aforementioned distortions is formulated and leads to an iterative solution. Given the mismatch parameters, simulation outcomes validate the feasibility of this proposed framework and promise impressive performance benefits.

A Wearable Platform for Monitoring Wrist Flexion and Extension in Biomedical Applications Using Organic Transistor-Based Strain Sensors

In this paper, a wearable platform for monitoring the wrist flexion and extension is reported. Differently, from similar devices already presented in literature, organic field-effect transistors will be effectively employed as strain sensors. We propose a novel device, fabricated over flexible plastic substrates, and capable to operate at low voltages (≤2 V). Thanks to these properties, the proposed devices can be integrated into a custom-made Lycra® glove for wrist motion monitoring without affecting the naturalness of movements, and interfaced with a portable readout electronic module. The readout electronics is able to transduce the current variation in the transistor structure into a voltage signal, opportunely conditioned and converted for proper acquisition by the elaboration unit. Control software allows users to set different control signals, including sensor polarization and overall amplification, to carry out sensor calibration and to finally record and real-time signal visualization. A complete electrical characterization of fabricated strain sensors is reported, as well as the evaluation of their functionality when mounted on the glove. The readout circuit is described, with details about the analog front-end design and simulation. Finally, the correct functionality of the complete system is demonstrated by the experimental acquisition of wrist movements and resolution evaluation. Thanks to the intrinsic properties of organic electronics in terms of lightweight, the platform represents a valuable system for non-invasive, imperceptible, and comfortable evaluation of wrist motion in real time, thus being effective for different applications such as rehabilitation and occupational health.

A 2.55 NEF 76 dB CMRR DC-Coupled Fully Differential Difference Amplifier Based Analog Front End for Wearable Biomedical Sensors.

High input impedance, low noise, high common mode rejection ratio (CMRR), and ultralow power are the most important performance indicators in the design of analog front end (AFE) for wearable biomedical sensors. This paper presents a fully differential difference amplifier based AFE that employs dc-coupled input stage to increase the input impedance and improve CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body dc bias scheme is introduced to deal with the input dc offset. Implemented in 0.35μm CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9μW at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtain the distinct α-wave after eye blink from EEG recording.