Hardware Design Research Articles

An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm

ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

Sustainability by Efficiency: Energy Considerations in IoT Device Development

The widespread use of Internet of Things (IoT) devices has brought about an unparalleled level of connectedness, revolutionizing several sectors and everyday existence. However, there are serious worries over the energy usage and environmental effect of these devices due to their increasing deployment. The urgent problem of improving energy efficiency in Internet of Things devices is explored in this study abstract. Acknowledging the complex issues, we examine the condition of IoT device architecture at the moment, focusing on elements that lead to excessive energy usage. We examine cutting-edge techniques via an extensive examination, such as advanced computing paradigms like edge and fog computing, low-power hardware design, and energy-efficient communication protocols. The study also looks at case studies and tests conducted in the real world, providing concrete proof of the efficacy of various energy-saving strategies. Even with significant progress, issues with security, privacy, and scalability still exist. We address the trade-offs between performance and energy efficiency, highlighting the necessity of standardizing solutions. Promising future prospects are outlined in our article, such as the incorporation of block chain applications, revolutionary developments in battery technology, and renewable energy sources. The purpose of this study abstract is to direct researchers, industry practitioners, and policymakers towards sustainable solutions for reducing the energy footprint of Internet of Things devices by offering a thorough view of the present scenario and forward-looking tactics.

Space-Specific Mixing Excitation for High-SNR Spatial Encoding in Magnetic Particle Imaging.

Magnetic Particle Imaging (MPI) is a radiation-free tracer-based imaging technology that visualizes the spatial distribution of superparamagnetic iron oxide nanoparticles. Conventional spatial encoding methods in MPI rely on a gradient magnetic field with a constant gradient strength to generate a field-free point or line for spatial scanning. However, increasing the gradient strength can enhance theoretical spatial resolution but also lead to a decrease in the Signal-to-Noise Ratio (SNR) and sensitivity of the imaging system. This poses a technical challenge in balancing spatial resolution and sensitivity, necessitating intricate hardware design. To address this, we present a Space-Specific Mixing Excitation (SSME) technique for achieving high-SNR spatial encoding in MPI. By utilizing a dual-frequency excitation magnetic field with a non-homogeneous field strength, magnetic particles at each position generate unique intermodulation responses. By performing multi-channel acquisitions across the entire field of view, high SNR MPI signals can be acquired. When combined with reconstruction techniques based on system matrix, multi-dimensional SSME-MPI can be achieved. The effectiveness of the proposed method was validated through phantom and in vivo imaging experiments. The results demonstrate significant improvements in sensitivity (3.6-fold improvement) and spatial resolution (better than 1 mm) without any hardware modifications. These findings demonstrate the capability of SSME to enhance both the spatial resolution and sensitivity of MPI. This method provides a solution to the ongoing challenge of balancing spatial resolution and sensitivity in MPI, potentially facilitating the implementation of MPI in a wider range of medical applications.

Design of RISCV processor using verilog

The main goal of this paper is to develop a 32-bit pipelined processor with several clock domains based on the RISCV (open source RV32I Version 2.0) ISA. To minimize the complexity of the instruction set and speed up the execution time per instruction, a RISC (Reduced Instruction Set Computer) processor that uses less hardware than a CISC (Complex Instruction Set Computer) is used. Furthermore, this paper constructed this processor with five levels of pipelining with the aid of necessary block diagrams, and all of the processes are well described. In this paper, a RISCV processor is designed and simulated using Verilog. The design of the RISCV processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISCV processor will be using 5-stage pipeline techniques to improve the overall performance of the processor. This system is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA, and forwardMuxB. Besides, a hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using Xilinx Vivado software.

Удобрения пролонгированного действия — новый этап развития рынка удобрений (обзор)

The review shows relevance and advantages of the application of prolonged action fertilizers, describes the methods of their producing and the hardware design of processes, suggests the classification of these fertilizer, developed by the authors, describes the main properties and methods for determining the quality indicators of such products.

Pilot Experiments and Hardware Design of Smart Electrooculographic Headband for People With Muscular Paralysis

Pilot Experiments and Hardware Design of Smart Electrooculographic Headband for People With Muscular Paralysis

Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool with High-Accuracy and Multi-Level Parallelism.

AutoDock Vina (Vina) stands out among numerous molecular docking tools due to its precision and comparatively high speed, playing a key role in the drug discovery process. Hardware acceleration of Vina on FPGA platforms offers a high energy-efficiency approach to speed up the docking process. However, previous FPGA-based Vina accelerators exhibit several shortcomings: 1) Simple uniform quantization results in inevitable accuracy drop; 2) Due to Vina's complex computing process, the evaluation and optimization phase for hardware design becomes extended; 3) The iterative computations in Vina constrain the potential for further parallelization. 4) The system's scalability is limited by its unwieldy architecture. To address the above challenges, we propose Vina-FPGA-cluster, a multi-FPGA-based molecular docking tool enabling high-accuracy and multi-level parallel Vina acceleration. Standing upon the shoulders of Vina-FPGA, we first adapt hybrid fixed-point quantization to minimize accuracy loss. We then propose a SystemC-based model, accelerating the hardware accelerator architecture design evaluation. Next, we propose a novel bidirectional AG module for data-level parallelism. Finally, we optimize the system architecture for scalable deployment on multiple Xilinx ZCU104 boards, achieving task-level parallelism. Vina-FPGA-cluster is tested on three representative molecular docking datasets. The experiment results indicate that in the context of RMSD (for successful docking outcomes with metrics below 2Å), Vina-FPGA-cluster shows a mere 0.2% lose. Relative to CPU and Vina-FPGA, Vina-FPGA-cluster achieves 27.33× and 7.26× speedup, respectively. Notably, Vina-FPGA-cluster is able to deliver the 1.38× speedup as GPU implementation (Vina-GPU), with just the 28.99% power consumption.

Self-Checking Hardware Design for Montgomery Exponentiation-Based Cryptography

Self-Checking Hardware Design for Montgomery Exponentiation-Based Cryptography

Hardware Design of Lightweight Binary Classification Algorithms for Small-Size Images on FPGA

Hardware Design of Lightweight Binary Classification Algorithms for Small-Size Images on FPGA

XSBench on FPGAs using Intel oneAPI

Field-Programmable Gate Arrays (FPGAs) are becoming an interesting component for heterogeneous computing systems in the post-Moore era thanks to their reconfigurable nature. The current generation of FPGAs includes specialized hard blocks for floating point operations, making them attractive for scientific computing. FPGA programming has historically been done in hardware description languages, which required a deep understanding of hardware design. Emerging high-level synthesis tools, such as Intel oneAPI and AMD Vitis™, provide a more common programming environment for FPGAs. In this paper, we explore the capabilities of FPGAs for acceleration in the context of nuclear particle transport simulators. As a case study, we implement XS-Bench in Intel oneAPI targeting FPGAs, including basic optimizations. We then compare the performance of Intel Stratix10 FPGA and Intel Xeon CPU-based systems and evaluate the viability of FPGA use in heterogeneous systems.

Unif-NTT: A Unified Hardware Design of Forward and Inverse NTT for PQC Algorithms

Unif-NTT: A Unified Hardware Design of Forward and Inverse NTT for PQC Algorithms

Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative

Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative

РАЗРАБОТКА МЕХАТРОННОГО МОДУЛЯ УЗЛА КРИОКОНЦЕНТРАТОРА КАРУСЕЛЬНОГО ТИПА ДЛЯ ОБЕСПЕЧЕНИЯ ПРОМЫШЛЕННОЙ БЕЗОПАСНОСТИ ПРИ СОЗДАНИИ НОВЫХ ПРОДУКТОВ ГЛУБОКОЙ ПЕРЕРАБОТКИ

A by-product in the production of cheeses, cottage cheese or casein is whey. According to the data provided by the International Dairy Association, about 50 % of the 140 million tons of world whey production are disposed of as production waste, which significantly reduces the economic efficiency of the industry. The most modern method of processing whey is cryoconcentration, which consists in the crystallization of moisture followed by displacement of the solid phase. Not improving the cryoconcentration process and its hardware design hinders the introduction of this method into production. In order to increase the productivity of the method of cryoconcentration of whey, a new design of a carousel-type cryoconcentrator with recovery was developed. To reduce the entrainment of the target components and to determine the nature of the crystallization process on the cryoconcentrator plates, a series of experiments were carried out to establish rational process parameters. This made it possible to develop a mechatronic cryoconcentration module for a carousel-type apparatus.

Efficient Hardware Design of DNN for RF Signal Modulation Recognition Employing Ternary Weights

Efficient Hardware Design of DNN for RF Signal Modulation Recognition Employing Ternary Weights

On Hardware Flexibility and Heterogeneity: A Vision for Monte Carlo Codes on Incoming RISC-V Computing Devices with AI-based Cross Section

As an open-sourced instruction set and being flexible in hardware extension, RISC-V begins its pace to enter the world of high performance computing. One of the distinguished feature of processing units adopting RISC-V is its ability to add custom circuits with special purpose accelerators. As the artificial general intelligence becomes practical, AI accelerators become an indispensable part of computing devices, where RISC-V is a great fit for the CPU to glue accelerators together. A system of chip designed by Alibaba T-head is one of the early chip in the massive production adopting RISC-V CPU, where the CPU, named Xuantie-910, has a high performance design with 128-bit RISC-V vector processing units, which are designed for accelerating AI applications. OpenMC has been adapted to run on Xuantie-910. In the Monte Carlo method for reactor physics, fetching the neutron cross sections is the hotspot that takes the majority of the computational burden. The traditional point-wise cross sections are slow because of memory latency caused by accessing many nonconsecutive memory addresses. An AI model for cross section is hence proposed. With 2.2 KB of runtime size, the smallest in the published work, the data can be fetched entirely in the L1 cache during on-the-fly cross section evaluation through single memory read. The in-house AI model also covers the entire energy range, unlike only the resonance range is supported in previous work. So, the effects from memory latency is minimized. The average relative error in AI modeled U-238 elastic cross section is 0.6% from point-wise cross section. With a modified version of OpenMC on Apple M3 Max, for a VERA pin-cell problem, compared to the point-wise cross section, the adoption of AI modeled cross section reduces the total runtime by 7%, although the runtime for calculating U-238 elastic cross section causes 40% more runtime. The adoption of AI modeled U-238 elastic cross section leads to K-effective 302 pcm higher than the case of adoption of point-wise cross sections. Advantage of AI model has been verified. With AI modeled cross section, the neutron slowing down problems with pure elastic scattering on U-238 has been studied on Xuantie-910. The average relative error in 65,536 group fluxes is about 0.9% from using point-wise cross section. However, with accelerating with the 128-bit vector processing units, the performance degrades by 35%, because of the narrow 64-bit load and store interface to the vector register files. The performance with Al modeled cross section is about 1/4 of the case with point-wise cross sections. In addition, the 1,024-bit width Ara RISC-V vector processing has been used to study the cost of AI modeled cross section evaluation. Being able to access the open-sourced hardware design in SystemVerilog, cycle accurate circuit simulation is performed. Using the vector processing units, the cost is reduced to 65% of the case using scalar instructions. The 128-bit load and store interface to vector processing units is a major contributor to the speeding up. The width of the load and store interface to vector processing units should be the main optimization factor in chip design to accelerate the AI modeled cross section evaluation.

Hardware Trojan Detection using Graph Neural Networks

The globalization of the Integrated Circuit (IC) supply chain has moved most of the design, fabrication, and testing process from a single trusted entity to various untrusted third party entities around the world. The risk of using untrusted third-Party Intellectual Property (3PIP) is the possibility for adversaries to insert malicious modifications known as Hardware Trojans (HTs). These HTs can compromise the integrity, deteriorate the performance, and deny the functionality of the intended design. Various HT detection methods have been proposed in the literature; however, many fall short due to their reliance on a golden reference circuit, a limited detection scope, the need for manual code review, or the inability to scale with large modern designs. We propose a novel golden reference-free HT detection method for both Register Transfer Level (RTL) and gate-level netlists by leveraging Graph Neural Networks (GNNs) to learn the behavior of the circuit through a Data Flow Graph (DFG) representation of the hardware design. We evaluate our model on a custom dataset by expanding the Trusthub HT benchmarks trusthub1. The results demonstrate that our approach detects unknown HTs with 97% recall (true positive rate) very fast in 21.1ms for RTL and 84% recall in 13.42s for Gate-Level Netlist.

Hardware Design Scheme Based on EEG Signals

Hardware Design Scheme Based on EEG Signals

Collaboration between Embedded Hardware Design and Embedded Software Development

Collaboration between Embedded Hardware Design and Embedded Software Development

Design of water level detection monitoring system using fusion sensor based on Internet of Things (IoT)

River flooding is a condition when the water in a river overflows and exceeds its normal capacity, thereby flooding the surrounding area. This flood disaster has been a known problem for a long time and causes great damage in the affected areas. Flood events inRivers are influenced by many factors, such as climate change, rapid urbanization, inappropriate land use, ineffective water management patterns, as well as uncontrolled addition of hard soil surfaces. Flood conditions in rivers involve complex processes and are influenced by various factors components, such as rainfall, water flow, topography, vegetation, and many other factors. Therefore, this research is very urgent because it can help reduce the negative impacts of flooding, increase public safety, become a basis for decision making, save costs and resources and make a positive contribution to technological development. This study aims to create a prototype of a flood early warning system. The system is based on a wireless sensor network whose interconnections are connected by a star topology. Every node is a combination of several sensors (sensor fusion) that are related to detecting floods, such as: height sensors, water flow speed sensors and rainfall intensity sensors. Design of hardware (hardware) and software (software) will be done. A classification mechanism based on Fuzzy Logic will be used to estimate flood conditions based on existing data. Flood estimation will determine the time and distance of flood events that will occur. Several experiments in the laboratory will be carried out to determine the performance of the designed system.

Imcube: A static particle size analyzer for all shape types via advanced vision tools and integrated machinery

An integrated machinery to perform the analysis of particle size distribution through image processing formulations is presented. The product is comprehensive and flexible to many different industrial needs with a tailored hardware integration and design, which employs a set of sophisticated algorithms for the computational efficiency and accuracy. Compared to the traditional methods, the architecture is superior and provides significant impact as irregular and noncircular particles from a wide dimension spectrum can be analysed instantly, eliminating the need for significant manual effort with conventional trays with low accuracy. The reports are obtained through the built-in screen, mounted on the device, at customer specified detail level in addition to state-of-the-art presentations benefiting common statistics. The prediction performance, which is validated through industrial data, can further be developed for smaller particles, as a higher resolution camera implementation is necessary, with a heuristic algorithm to estimate the maximum likelihood of particle sizes when they overlap on the measurement tray.