Design For Testability Method Research Articles

Logic operation‐based Design for Testability method and parallel test algorithm for 1T1R crossbar

Among resistive random access memory (RRAM) architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. For 1T1R crossbar, a logic operation-based Design for Testability and parallel test algorithm, which is an improvement of March C*-1T1R test algorithm, are proposed. The pass-fail fault dictionary of the proposed test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors and traditional RAM. Compared with March MOM, March C* and March C*-1T1R, the test time of the proposed test algorithm is reduced with a little area overhead for a large size crossbar.

Improve Productivity through Reducing MBT Application Time Using Multi Bad Block Management DFT

Recently, storage market has been shifting from hard disk to SSD, and the importance of NAND flash memory, which plays a key role as a storage media in the SSD, is also increasing. Accordingly, in the manufacturing phase, the test cost of NAND flash memory is getting larger as the density of NAND flash memory is increasing. In this paper, we propose a scheme for DFT(Design for Testability) that can reduce the NAND flash test cost and apply it to the actual MBT(Monitoring Burn-in Test) manufacturing process to prove improvements in the manufacturing cost. There are 3 steps (DC/MBT/POB) between package process and shipment. The purpose of 3 steps is to evaluate the characteristics and to ensure the reliability. MBT equipment stresses to induce early failure of marginal devices in amount of time at hot temperature. Therefore we can reduce defective products in early stage. MBT is essential process in manufacturing NAND flash memory. Therefore, reducing MBT process cost has been a big issue. Using the characteristics of MBT application and NAND flash memory, the DFT method is devised. NAND flash memory always has bad blocks as part of the total blocks. User can not use bad blocks. Therefore it is necessary routine to manage bad blocks when devices are tested. MBT equipment consists of 48 slots and each slot has 64ea I/O channels. If a device has 8ea I/O pins, it can be tested just 8ea devices per slot concurrently. In order to test more than 8ea devices each slot, the test should be conducted in several times. This concept is called “scan”. Increasing test time is caused by increasing the total scan times in accordance with MBT structural problems. Scan and slot structure acts as a factor enabling the massive quantity test. Thus the total scan loop times take up a large portion MBT application time, we are studying ways to reduce the total scan loop times. We devised a DFT method for managing bad block efficiently. This DFT method is called multi bad block management, the details are as follows. Previously in order to find bad blocks, MBT equipment loops scan at every single block to determine pass or fail. We suggest that the newly proposed method is storing pass/fail data of multiple blocks in NAND flash memory internal register. And it is added to the accumulator to determine pass/fail of every multiple blocks rather than single block. It is possible that scan doesn`t loop not single block but every multiple blocks. As a result, it can reduce total scan loop times as follows. As is : (The Number of Total Blocks) x Scan Loop To be : (The Number of Total Blocks/64) x Scan Loop There are a large number of internals latches for pass /fail in NAND flash memory. Toggling RE(read-enable) signal outputs continuously multiple blocks Pass/Fail bit which is stored in the latch. It reduces the scan loop times of MBT, which can reduce system time. It enables test cost reduction and increases productivity due to reduced overall test time, and improves test efficiency. Status parity of 64ea blocks pass/fail parity are stored in chip for shorten the test time in MBT process. When applied to 128Gb NAND flash memory, we could reduce from 21.5 hours to 18.5 hours about 14% test time. If there are more the pass/fail latches, it can further reduce the test time. However because of the area overhead, we limit to status of 64ea blocks. With multi bad block management DFT techniques, we can reduce NAND flash memory test cost of the SSD. Also, if applied products are developed in the future, it is expected to continue to be able to see the effect.

A Testable Design Method for Memories by Boundary Scan Technique

This paper presents a design for test the embedded flash in an object System-on-a-chip (SoC). The feature of the Flash TAP (Test Access Port) complies with the IEEE std.1149.1, and it can select different scan chains and other control registers for other test. By the trade-off between the test time and the circuit area, an IST (In System Test) circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small testing timing by the use of IST.

Evaluation of testability enhancement using software prototype

The functional delay-fault models, which are based on the input stimuli and correspondent responses at the outputs, cover transition faults at the gate level quite well. This statement forms the basis for the analysis and comparison of different methods of design for testability (DFT) using software prototype model of the circuit and to select the most appropriate one before the structural synthesis of the circuit. Along with known DFT methods (enhanced scan, launch-on-shift scan and launch-on-capture scan), the authors introduce the method, which is based on the addition of new connections to the circuit in the non-scan testing mode. In order to assess the DFT methods, the functional test is generated for the analysed circuit and the functional delay-fault coverage for this test is evaluated. Each of the considered DFT methods has its own advantages and disadvantages, since they have different delay fault coverage, and require different hardware for their implementation. These differences depend on the function of circuit. The experimental results are provided for the ITC'99 benchmark circuits. The obtained results proved the applicability of the proposed method.

Electrical Test Method for Interconnect Open Defects in 3D ICs

In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz.

A New Design-for-Testability Method Based on Thru-Testability

Partial scan and non-scan techniques allow test generation of high fault coverage for sequential circuits with less area overhead and less performance degradation than full scan technique. In most of these techniques, extra logic (e.g. a multiplexer introduced by partial scan) is added to permit a data transfer from a flip-flop (or input) to another flip-flop (or output). Such additional logic function is called thru function in this paper, which plays an essential role in enhancing the testability of a circuit. In this paper, we introduce a design-for-testability (DFT) technique which modifies a given sequential circuit to a thru-testable sequential circuit with acyclic test generation complexity by adding new thru functions based on the information of thru functions that may exist in the original design and the dependency among these thru functions. Thus, thru functions of a given sequential circuit should first be extracted from its high-level description. If there is a thru function that transfers data from a flip-flop to another flip-flop, the latter is exempted from being considered in DFT insertion. This reduces the additional logic to be added. Using ITC'99 benchmark circuits, we show that the proposed DFT method takes up less area overhead compared to the previous scan methods in testing the difficult-to-test circuits like b07, b08 and b15. Besides, the test application time is shorter than that of previous scan methods while the test data volume is less too in difficult-to-test circuits.

F-Scan: A DFT Method for Functional Scan at RTL

Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.

Ultra-fast CAD scan chain highlighting for failure analysis assistance

Automatic test pattern generation (ATPG) and scan tests are common design for testability methods (DfT) for digital logic ICs. A prerequisite for structural logic tests is the integrity of the embedded test circuit itself, i.e. the scan flipflops that are stringed together in scan chains. If there is a failure within one of the scan chains, localization can be quite challenging. One particular problem for failure analysis engineers is the CAD navigation along the chain: in order to display the physical position of a scan chain, hundreds or even thousands of flipflops have to be cross-mapped between the design netlist and the physical layout. This task requires extensive computing and can be very time-consuming. The work described in this paper is a new data processing method that reduces the required computing time from several hours down to a few seconds.

A New Class of Easily Testable Assignment Decision Diagrams

This paper introduces a new class of assignment decision diagrams (ADD) called thru-testable ADDs based on a testability property called thru function. The thru-testable ADDs is an easily-testable set of thru functions that allows data transfer from its input to its output. We also define a design-for-testability (DFT) method to augment a given ADD with thru functions so that the ADD becomes thru-testable. We compare the circuits modified using our proposed method with the original circuits and partial scan designed circuits in terms of fault efficiency, area overhead, test generation time and test application time. Since the proposed DFT method is introduced at a high level, which deals with less number of gates, the information of thru functions can be extracted more easily. As a result, it lowers the area overhead compared to partial scan.

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC?99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.

Non-scan Design for Single-Port-Change Delay Fault Testability

We propose a non-scan design-for-testability (DFT) method at register-transfer level (RTL) based on hierarchical test generation: the DFT method makes paths in a data path single-port-change (SPC) two-pattern testable. For combinational logic in an RTL circuit, an SPC two-pattern test launches transitions at the starting points of paths corresponding to only one input port (an input, which has some bits, of an RTL module) and sets the other ports stable. Hence, during test application, the original hold function of a register can be used for stable inputs if the hold function exists. Our DFT method can reduce area overhead compared to methods that support arbitrary two-pattern tests without losing the quality of robust test and non-robust test. Experimental results show that our method can reduce area overhead without losing the quality of test. Furthermore, we propose a method of reducing over-test by removing a subset of sequentially untestable paths from the target of test.

Advances in VLSI testing at MultiGb per second rates

Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability) methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment) resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator) patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

A nonscan DFT method for RTL circuits based on fixed‐control testability

AbstractIn this paper, we will newly define the fixed‐control testability as the property of the data paths for which the hierarchical test generation is easy; and based on it we will propose a design for testability (DFT) method for register transfer level (RTL) circuits. In the proposed method, since it is based on the hierarchical test generation using combinational test generation method and nonscan design, the test generation time and test execution time can be shortened drastically compared to the full‐scan design method, and the test at real operation speed (at‐speed test) is possible; and the complete fault detection efficiency can be guaranteed. Moreover, the effectiveness of the proposed method will be shown by experiments using benchmark circuits. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(10): 43–55, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10119

Handling the pin overhead problem of DFTs for high-quality and at-speed tests

The pin overhead problem of nonscan design for testability (DFT) and built-in self-test design has been an unsolved problem for a long time. A new algorithm is proposed to connect extra pins of control test points with primary inputs. An economical test point structure is introduced, in which only one gate delay is added to the corresponding functional paths inserted into a control test point. Unlike almost all of the previous nonscan DFT methods which do not handle pin overhead well, this method allows at most three extra pins. Techniques are presented to connect an extra input of a control test point to a primary input in order to avoid conflicts produced by the newly generated reconvergent fanouts. Similar techniques are proposed to connect more than one control input with the same PI. Sufficient experimental results are presented to demonstrate the effectiveness of the method.

Primitive delay faults: identification, testing, and design for testability

We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first propose a new technique to identify and test primitive faults. A primitive fault is a path delay fault that has to be tested to guarantee the performance of the circuit. Primitive faults can consist of single- (SPDF's) or multiple path delay faults (MPDF's). Testing strategies for single primitive faults exist. In this paper, we focus on identifying and testing multiple primitive faults. Identification and testing of these faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the SPDF model, and (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The SPDF's contained in a multiple primitive fault have to merge at some gate(s). Our methodology can quickly (1) rule out a large number of gates as possible merging gates for primitive faults, and (2) prune the combinations of paths that can never belong to any primitive fault. Our identification procedure also finds a test for the fault. We present a complete algorithm for identifying and testing double path delay faults, Identifying and testing all primitive faults is impractical for large designs. This is because no efficient methods are known for testing primitive faults that include a large number of paths. However, to guarantee that the performance of a digital circuit is not affected by timing defects, it is necessary to test all primitive faults. Our second contribution is a new design for testability method. Our method guarantees that only primitive faults with at most two paths can exist in the circuit in the test mode. The main idea is to efficiently identify a small set of signals for inserting test points to eliminate primitive faults with more than two paths. Our test points only provide controllability. Addition of a single test point can lower the cardinality of several primitive faults. Our approach efficiently re-evaluates primitive delay fault testability of the circuit after insertion of a test point. After a few iterations only primitive faults with at most two paths can exist in the circuit in the test mode. Experimental results on several multilevel combinational benchmark circuits are included to demonstrate the usefulness of our techniques.

Concurrent test method for OTA-C filters

A new testable design method for OTA-C filters is presented. By comparing the currents consumed by the circuit under test (CUT) and the currents converted from the voltage levels of the CUT, abnormalities in the function of circuit components can be concurrently detected.

Design-for-test (DfT) study on a current mode DAC

The integration of design-for-test (DfT) features into complex integrated circuits (ICs) to support exhaustive, fast, and therefore economic testing is becoming crucial to the manufacturing process. The authors investigate the effectiveness of two different test strategies for a current-mode digital-to-analogue converter (DAC) and DfT methods for optimising the design at the transistor level. The first approach is a standard functional test; the second, a novel parametric test strategy with on-chip support. Both strategies are supplemented by an Issq screen for the digital components. The evaluation process used to compare the effectiveness of these two test strategies shows that both approaches result in similar fault coverage figures and a number of simple circuit level design changes can enhance the fault coverage and reduce the size of the test set.