Design For Debug Research Articles

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty

Due to limited on-chip caching, data-driven applications with large memory footprint encounter frequent cache misses. Such applications suffer from recurring miss penalty when they re-reference recently evicted cache blocks. To meet the worst-case performance requirements, Network-on-Chip (NoC) routers are provisioned with input port buffers. However, recent studies reveal that these buffers remain underutilised except during network congestion. Trace buffers are Design-for-Debug (DfD) hardware employed in NoC routers for post-silicon debug and validation. Nevertheless, they become non-functional once a design goes into production and remain in the routers left unused. In this article, we exploit the underutilised NoC router buffers and the unused trace buffers to store recently evicted cache blocks. While these blocks are stored in the buffers, future re-reference to these blocks can be replied from the NoC router. Such an opportunistic caching of evicted blocks in NoC routers significantly reduce the miss penalty. Experimental analysis shows that the proposed architectures can achieve up to 21 percent (16 percent on average) reduction in miss penalty and 19 percent (14 percent on average) improvement in overall system performance. While we have a negligible area and leakage power overhead of 2.58 and 3.94 percent, respectively, dynamic power reduces by 6.12 percent due to the improvement in performance.

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost

In this paper, a design for debug (DFD) method that reuses test resources is proposed to reduce the debug cost in post-silicon validation. With the proposed method, the trace buffer is shared for embedded cores to capture the signatures of each core concurrently by reusing a test access mechanism. In this case, the depth of the trace buffer allocated to the core is reconfigurable and variable according to debug scheme. The experimental results indicate that the proposed DFD significantly reduces the debug time when the trace buffer is shared by cores in various debug cases.

On a New Mechanism of Trigger Generation for Post-Silicon Debugging

The main goal of post-silicon debugging is to locate errors undetected during the pre-silicon verification. Although high speed of hardware prototype can be leveraged to expedite running a large number of realistic test vectors, the low level of observability and controllability of signals inside a prototype is a big concern. Design for Debug (DFD) techniques aim to improve the observability of signals and speed up the root-cause analysis of errors. Incorporation of an Embedded Logic Analyzer (ELA) is introduced as one of the practical DFD techniques. An ELA contains a trigger unit that controls conditions for which trace signals should be captured in a buffer for post-processing. In this paper, we propose a tool to generate hierarchical triggers, providing compact trace information for root-cause analysis. Major advantages of our technique as a means to generate trigger units are: 1) failure localization and root-cause analysis is expedited by keeping the hierarchical trace of interactions leading to failures, 2) overlapped failure patterns can be found by mechanism which results in a 60-65% reduction in hardware overhead compared to the previously proposed method, 3) it can be parameterized to generate several units, making it possible to incorporate checkers into scarce silicon area and enabling on-chip debugging by means of time-multiplexing scheme.

Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

Rapid growth in size and complexity of modern SoCs results in numerous architectural changes in design for test (DFT) and design for debug (DFD). Understanding the challenges and tracking the advances in DFT and DFD (DFx) design and architecture are essential for correct architecture planning of the next generation of SoCs. This paper provides an insight into the evolution of Graphics Northbridge (GNB) DFx architectures across four generations of AMD Application Specific Integrated Circuit (ASIC), including the first AMD fusion accelerated processor unit (APU).

Deterministic Replay Using Global Clock

Debugging parallel programs is a well-known difficult problem. A promising method to facilitate debugging parallel programs is using hardware support to achieve deterministic replay on a Chip Multi-Processor (CMP). As a Design-For-Debug (DFD) feature, a practical hardware-assisted deterministic replay scheme should have low design and verification costs, as well as a small log size. To achieve these goals, we propose a novel and succinct hardware-assisted deterministic replay scheme named LReplay. The key innovation of LReplay is that instead of recording the logical time orders between instructions or instruction blocks as previous investigations, LReplay is built upon recording the pending period information infused by the global clock. By the recorded pending period information, about 99% execution orders are inferrable, implying that LReplay only needs to record directly the residual 1% noninferrable execution orders in production run. The 1% noninferrable orders can be addressed by a simple yet cost-effective direction prediction technique, which further reduces the log size of LReplay. Benefiting from the preceding innovations, the overall log size of LReplay over SPLASH-2 benchmarks is about 0.17B/K-Inst (byte per k-instruction) for the sequential consistency, and 0.57B/K-Inst for the Godson-3 consistency. Such log sizes are smaller in an order of magnitude than previous deterministic replay schemes incurring no performance loss. Furthermore, LReplay only consumes about 0.5% area of the Godson-3 CMP, since it requires only trivial modifications to existing components of Godson-3. The features of LReplay demonstrate the potential of integrating hardware support for deterministic replay into future industrial processors.

On-Chip Support for NoC-Based SoC Debugging

This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based system-on-chips (SoCs). We present a test wrapper and, a test and debug interface unit. They enable data transfer between a tester/debugger and a core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate test and debug. We also present a novel core debug supporting logic to enable transaction- and scan-based debug operations. The basic operations supported by our scheme include event processing, stop/run/single-step and selective storage of debug information such as current state, time, and debug event indication. This allows internal visibility and control into core operations. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead.

Functional Debug Techniques for Embedded Systems

Some problems in a new chip design or its embedded software show up only when a silicon prototype of the chip is placed in its intended target environment and the embedded software is executed. Traditionally, embedded-system debug is very difficult and time-consuming because of the intrinsic lack of internal system observability in the target environment. Design for debug (DFD) is the act of adding debug support to a chip's design in the realization that not every silicon chip or embedded-software application is right the first time. In the past few years, functional debug has made significant progress. This article describes the most common structured approaches available for silicon debug of embedded systems.

Design for debug: catching design errors in digital chips

For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chip's features accessible through a serial interface.

Design for Debug

For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which...