Derivative Superposition Method Research Articles

A +7.6 dBm IIP3 2.4-GHz Double-Balanced Mixer With 10.5 dB NF in 65-nm CMOS

In this brief, an enhanced derivative superposition (DS) method is proposed to increase the third-order input intercept point (IIP3) of double-balanced CMOS active mixers. In the proposed mixer, an auxiliary common-gate transconductor biased in the moderate inversion region with a source inductive degeneration is used in the feedforward AC-coupled path to the main transconductor to generate the third-order intermodulation distortion (IMD3) current. Hence, the overall IMD3 current of the transconductance stage is minimized while optimizing the conversion gain (CG). This auxiliary transconductor also improves the overall NF of the mixer by partially cancelling the output noise voltage. In addition, the current reuse and current bleeding techniques are utilized to further improve the overall performance. As a proof-of-concept, a 2.4-GHz down-conversion mixer with an output bandwidth of 10 MHz is implemented in a 65-nm CMOS process. Measurement results show that the mixer achieves a peak CG of 12.5 dB, a double-sideband (DSB) noise figure (NF) of 10.5 dB, and IIP3 of +7.6 dBm. The circuit consumes 1.2 mW from a 1-V supply and excluding the pads, it occupies a silicon area of 0.2208 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.3–6 ​GHz noise and distortion cancelling LNA achieving an NF of 2.8±0.3 ​dB in 0.18-μm SiGe BiCMOS process

This paper presents a noise and distortion cancelling wideband low-noise amplifier (LNA) in JAZZ 0.18-μm SiGe BiCMOS process. In the proposed design, a shunt feedback (SFB) and a common-emitter (CE) paths are adopted to reduce the dominant noise contribution of the main path. To enhance the linearity, the derivative superposition method is modified to eliminate the whole nonlinearity components. Moreover, with the help of an n-type MOS acted as a resistive load of the CE path, both flat gain and acceptable output impedance matching are achieved. The measurement results exhibit that the LNA has an input third-order intercept point (IIP3) of −4 dBm with a noise figure (NF) of 2.8 ​± ​0.3 ​dB and a power gain 16.5 ​± ​0.2 ​dB from 0.3 to 6 ​GHz. The circuit draws 14.5 ​mA dc current from a 3.3 ​V supply for core area of 0.22 ​mm2.

A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

APPLYING THE DERIVATIVE SUPER POSITION METHOD FOR A HIGH LINEAR COMMON SOURCE CMOS POWER AMPLIFIER IN ULTRA-WIDEBAND APPLICATIONS

The problem with the power amplifiers is that raising the gain and output power may affect the other amplifier factors specially in the frequency ultra-band. This paper presents a CMOS power amplifier (PA) for Ultra-Wideband (UWB) applications in 2.2 to 5 GHz using two stages of common source topology with derivative superposition (DS) method. Simulation results show an average power gain of27.2 dB with an input 1dB compression point (1dB-CP) of -14.6 dBm at 3.2 GHz and an output 1dB compression point (1dB-CP) 12.9 dBm. With an input power of 83.8 mW, from a 1.8 V supply, power added efficiency (PAE) is 47.5% at 3.2 GHz with 50Ω load impedance and stability factor is 7.2 at 3.2GHz. The proposed design has been simulated using TSMC 0.18µm technology. The important parameters that define an RF Power Amplifier are: Output Power, Gain, Linearity, Stability, DC supply voltage, Efficiency, Ruggedness. The design results showed high power output without affecting the other amplifier factors. A comparison with the previous research has been done and the comparison is clearly in favor of the present design.

Tunable linearity enhancement for 180 nm complementary metal–oxide–semiconductor LNA with active feedback

The authors present a tunable linearity improvement of complementary metal–oxide–semiconductor low-noise amplifier (LNA) using derivative superposition method and an active MOS field-effect transistor feedback transistor. The proposed LNA achieves a third-order input intercept point (IIP3) of 21 dBm, 9.43 dB gain, and 2.4 dB minimum noise figure. In addition, the proposed LNA method dissipates 28.4 mW supplied from 1.8 V voltage source. The proposed LNA provides flexibility to tune the power dissipation and linearity according to the work environment. They perform the simulation with keysight ADS2016.01 software utilising 180 nm TSMC model files.

A 5 dB NF 100 KHz 1/F corner and 35 dBm OIP3 down conversion mixer using dynamic current injection and derivative superposition method

This letter presents the design and measurement of high OIP3, low flicker noise double-balanced Gilbert cell down conversion mixer in CMOS process. The key features of proposed mixer are dynamic current injection and derivative superposition. Since the flicker noise (1/f noise) have a strongly affect mixer's noise figure (NF), a dynamic current injection is used to reduce the flicker noise. The derivative superposition method has an auxiliary common gate stage of radio-frequency (RF) input stage to cancel each third order intermodulation distortion (IMD3) and can provide a high third order output intercept point (OIP3). The proposed down conversion mixer is fabricated in 0.18 μm CMOS technology. And this letter highlights the performances of the proposed mixer in terms of: flicker noise (i.e., noise figure: 5 dB at 100 kHz), third order output intercept point (i.e., OIP3, typically 35 dBm), and the conversion gain (i.e., typ. 17.3 dB) from −20 dBm RF input at 2.4 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1720–1723, 2016

A Highly Linear Low Noise Amplifier With Wide Range Derivative Superposition Method

This letter presents an L-band highly linear differential low noise amplifier (LNA) in a standard 90-nm CMOS process. A wide range derivative superposition technique is proposed to maximize the third-order intercept point (IP3), and at the same time, minimize the third-order intermodulation distortion (IMD3) over a wide input power range. The LNA chip achieves a measured OIP3 of $+33.7~{\rm dBm}$ and IMD3 of $-65~{\rm dBc}$ with $-15~{\rm dBm}$ input power. The measured peak gain and minimum noise figure are 15.4 dB and 1.36 dB at 1.27 GHz, respectively. The LNA chip consumes 40 mA from a 3.3-V supply.

Source Degenerated Derivative Superposition Method for Linearizing RF FET Differential Amplifiers

The second-order interaction effect in a field-effect transistor (FET) differential amplifier is analyzed using the Volterra series analysis method. The analysis results reveal that the second-order interaction is inherent in the fully differential amplifier structure, and thus can never be cancelled out. In contrast, it is found that the second-order interaction is possibly cancelled out by adding source degeneration impedance in the pseudodifferential amplifier (PDA) structure. In addition, the second-order interaction cancellation condition in the PDA can be made more robust and wider over the input signal swing by adopting the derivative superposition (DS) method. By combining the second-order interaction cancellation technique and the DS technique, a differential source degenerated DS method is proposed for linearizing FET differential amplifiers. A 2-GHz differential amplifier based on the proposed structure is designed for a power amplifier driver in an RF transmitter. Fabricated in 0.13-μm CMOS, it operates from a 1.2-V supply with the power dissipation of 30.2 mW. Measurement results show that it achieves +30.4 dBm of peak output third-order intercept point, 43 dBc of C/I at 0-dBm output power, +9.7 dBm of output-referred P1dB, and +10.6 dB of power gain.

A CMOS 3.1 - 10.6 GHz UWB LNA Employing Modified Derivative Superposition Method

Low noise amplifier (LNA) performs as the initial amplification block in the receive path in a radio frequency (RF) receiver. In this work an ultra-wideband 3.1 10.6-GHz LNA is discussed. By using the proposed circuits for RF CMOS LNA and design methodology, the noise from the device is decreased across the ultra wide band (UWB) band. The measured noise figure is 2.66 3 dB over 3.1 10.6-GHz, while the power gain is 14 ± 0.8 dB. It consumes 23.7 mW from a 1.8 V supply. The input and output return losses (S11 & S22) are less than –11 dB over the UWB band. By using the modified derivative superposition method, the third-order intercept point IIP3 is improved noticeably. The complete circuit is based on the 0.18 μm standard RFCMOS technology and simulated with Hspice simulator.

Linearity improvement of 5.2-GHz CMOS up-conversion mixer for wireless applications

This letter presents linearity improvement up-conversion mixer at 5.2 GHz for wireless applications. The design is based on Gilbert-cell active double-balanced mixer using derivative superposition method for linearity improvement. The design improvement is proposed in TSMC 0.18-μm CMOS process. The linearity of the designed mixer is further improved using source degeneration inductors at transconductors stage. The measurement results indicate that the proposed method shows the third-order intercept point (IIP3) of 13.5-dBm, which is higher than previously published mixers. The mixer achieves the conversion gain of 2 dBm, and consumes 3.0 mA at 1.8 V power supply. The size of the whole chip is 0.56 mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:923–925, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26711

Linearity improvement using a modified derivative superposition method in cascaded stages amplifier

A modified derivative superposition (DS) method using cascaded stages transistor is described. It uses the third order intermodulation (IMD3) current generated from the preceding stage to cancel those at the output of the following stage. This analysis demonstrates that an IMD3 minimum occurs near the output power compression point. A balanced X-band linear power amplifier (PA) monolithic microwave integrated circuit (MMIC) using this concept is presented. The results of measurement showed a carrier-to-IMD3 ratio (C/I3) improvement more than 30 dB compared with the conventional cascaded stages configuration.

A High Linearity Folded Gilbert Mixer for 2.4GHz Application

A 2.4GHz high linearity downconversion mixer is designed with MOSFET transconductance linearization technique. Multiple gated transistors (MGTR) (or derivative superposition) method is adopted in the structure to increase IIP3 of the mixer as well as its convertion gain isn’t degraded. In order to improve the performance of the mixer further, a LC tank is used in the LO stage and two current steering PMOS transistors in load stage. The Mixer is design in TSMC 0.35um SiGe BiCMOS technology. Simulation results show that the mixer achieves 2.88dBm input 1dB compress point, 16.18dBm third-order input intercept point (IIP3) and the conversion gain is 12.97dB.

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.

Linearity improvement of cascode low-noise amplifiers using double DS method with a tuned inductor

We propose a highly linear low-noise amplifier (LNA) using the double derivative superposition method with a tuned inductor. This topology has an auxiliary common gate stage of the cascode amplifier to cancel each third-order intermodulation distortion (IMD3) component and can provide a high third-order input intercept point (IIP3) for the 5.25 GHz frequency band. From the simulation results using the TSMC 0.18 μm RF CMOS process, the IIP3 in the proposed cascode LNAs can be improved by 9 dB, compared with the conventional derivative superposition method. The proposed LNA achieves an IIP3 of + 15 dBm with a gain of 10.5 dB, a noise figure of 2.4 dB, and a power consumption of 6 mA at 1.5 V.

Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology

Abstract:In this paper, we present a fully integrated CMOS LNA (low noise amplifier) with inputmatching LC ladder technique circuitry to cover the upper band of UWB from 3.1 to 10GHz. Also, an improved technique of derivative superposition (DS) method is proposedto improve the linearity by using both forward body bias technology, and currentreused.The proposed LNA can operate at reduced supply voltage and powerconsumption. This configuration provides better input matching, lower noise figure, andmore reverse isolation which is vital in LNA design. Complete analytical simulation ofthe circuit results in frequency of 3.1 GHz to 10 GHz, with 2.44 dB NFMIN, 50Ω inputimpedance, 13.5dB peak power gain (S21), high reverse isolation (S12) -50 dB, -15dBinput matching (S11) and -10dB output matching (S22), while dissipating as low poweras1.5mW low supply voltage of 0.6 V.

A Fully Integrated 3.3–3.8-GHz Power Amplifier With Autotransformer Balun

This paper demonstrates the usage of a differential autotransformer as an output balun for an integrated power amplifier (PA) operating at low-gigahertz frequencies. In comparison with a conventional transformer balun, an autotransformer balun offers lower power losses, thereby increasing the saturated output power and reducing the gain compression at the edge of target power range. A theoretical analysis of an integrated autotransformer is given, comparison with a magnetic transformer is performed. The concept was experimentally verified in a fully integrated PA for a 3.3-3.8-GHz WiMAX band fabricated in SiGe : C bipolar technology. The active part of the amplifier implements the derivative superposition method aimed at linearizing the power transfer characteristic. Measured PA delivers saturated output power above 29 dBm. The maximum achieved power-added efficiency exceeds 40% at 3.4 GHz. At 3.5 GHz, 1-dB gain compression occurs for P out = 24.6 dBm.

Robust derivative superposition method for linearising broadband LNAs

A linearisation methodology for broadband low noise amplifiers (LNAs) is considered. The proposed scheme is composed of the main transistor operating in strong inversion healed by a couple of auxiliary transistors operating in triode and subthreshold regions. The nonlinearities of these transistors graciously and efficiently compensate each other, improving main transistor linearity by over 10 dB over all corners for input signals as large as −14 dBm. Power consumption increases by 6% while frequency response and input impedance are almost not affected because the compensating circuits are quite small compared with the main device. Simulation results show that the compensated LNA implemented in Jazz-Semiconductor 0.18 µm CMOS technology has a gain of 11.3 dB, IIP3=18.4 dBm, BW=3.6 GHz while drawing 7.4 mA from a 2.4 V supply voltage.

New implementation of high linear LNA using derivative superposition method

New implementation of a high linear low-noise amplifier (LNA) using the improved derivative superposition (DS) method is proposed. The input stage is formed by two transistors connected in parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the moderate inversion region instead of the weak inversion region, thus allowing a feasible source degeneration inductance at the sources of the two transistors to achieve a good input impedance matching and low noise figure (NF) while keeping high third-order input intercept point (IIP3) improvement with the DS method. The new implementation has been used in a 0.18-μm CMOS high linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB NF and 7.5 mA at 1.8 V power consumption.

Modified derivative superposition method for linearizing FET low-noise amplifiers

Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

Low-distortion MMIC power amplifier using a new form of derivative superposition

Reduction of interchannel interference produced by a power amplifier near 1-dB compression is a key concern for the wireless communications industry. In this paper, we present a 100-mW monolithic-microwave integrated-circuit (MMIC) power amplifier designed using a novel form of the derivative superposition method. The measured results of the MMIC power amplifier showed a two-tone carrier-to-interference (C/I) ratio of 45 dBc with an efficiency of 22.5% when backed off by 4.5 dB from the 1-dB compression point. We demonstrate that the MMIC power amplifier represents a good compromise between C/I ratio, output power, efficiency, and gain at the cost of an increase in total gate width, by comparing it to class-A, class-AB, and class-B single field-effect-transistor amplifiers.