Dependence Of Subthreshold Swing Research Articles

Performance optimization of nanometer-thin indium-tin oxide transistors by two-step air annealing

In this study, the influence of air annealing on nanometer-thin indium tin oxide (ITO) transistors was investigated. Compared with unannealed devices, the field-effect mobility and subthreshold swing of ultrathin ITO transistors with pre-annealing, post-annealing, and two-step annealing were greatly improved. Under a pre-annealing temperature at 200 °C and post-annealing temperature at 100 °C, the ultra-thin ITO transistors showed field-effect mobility of 34.2 cm2/Vs, steep subthreshold swing of 1.95 V/decade, and high Ion/Ioff ratio of 2.46 × 107. X-ray photoelectron spectroscopy revealed that the performance changes could be ascribed to the changes in the oxygen vacancies in the ITO channel under different annealing conditions. The dependence of subthreshold swing on the annealing process may be related to the absorption and release of water molecules from the ultrathin ITO surface. Overall, these results emphasize the importance of the annealing procedures for nanometer-thin ITO transistors.

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.

Revised Analysis of Design Options and Minimum Subthreshold Swing in Piezoelectric FinFETs

The theoretical limit of sub-threshold swing ( SS ) in the n-type piezoelectric FinFET (Piezo-FinFET) is thoroughly investigated. Gate voltage modulated strain, conduction band edge shift, and the SS are evaluated utilizing physics-based modeling and numerical simulation, indicating a strong dependence of SS on the fin width, crystalline orientation, and physical properties of the piezo-material used in the gate stack. For [001] Si and [111] Ge Piezo-FinFETs with 5-nm fin width and 3-nm PZT-5H thickness, SS values down to 40 mV/decade are achievable after design optimizations. A figure of merit, ${E}_{\text{cr}} {d}_{z3}/{S}_{\text{pie}, 33}$ , is proposed for the piezo-materials in terms of the critical electric field ( ${E}_\text{cr}$ ), the piezoelectric strain constant ( ${d}_{z3}$ ), and the elastic compliance constant ( ${S}_{\text{pie}, 33}$ ), to guide the Piezo-FinFET designs.

Performance Evaluation and Optimization of Single Layer MoS2Double Gate Transistors With Schottky Barrier Contacts

The making use of 2-D material as transistor channel is a rapid growth field since it can provide enough gate controllability for transistors at scaling limit. Among all kinds of 2-D materials, monolayer MoS2 stands out because of its large intrinsic bandgap and moderate mobility at room temperature. Most of the simulation work assumes the source/drain contacts of monolayer MoS2 transistors are Ohmic type, while in experiment the Schottky barrier contacts are more frequently seen. In this paper, the performance of single layer MoS2 double gate transistors with Schottky barrier contacts is evaluated with nonequilibrium Green’s function method. The image force lowering effect, which is crucial for accurate simulation of Schottky barrier, is taken into account. The simulation results reveal that increasing doping concentration is the most effective way to adjust monolayer MoS2 transistor performance. Transistor performance with Schottky barrier contacts can be comparable and even outperforms those with Ohmic contacts. The dependence of subthreshold swing, drain-induced barrier lowering and intrinsic delay on Schottky barrier height, source/drain extension length, and doping concentration in source/drain extension region are also simulated and analyzed. The effect of phonon scattering on performance of monolayer MoS2 transistor with Schottky barrier contacts and Ohmic contacts is also presented.

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both ${I}$ – ${V}$ and ${G}$ – ${V}$ characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: ${g}_{m}/{I}_{\text {d}}$ , ${g}_{m}/{g}_{ds}$ , ${f}_{T}$ and ${f}_{T}/{I}_{d}{V}_{d}$ , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to $40~\text {V}^{-1}$ , for currents lower than 10 nA/ $\mu \text{m}$ ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ $\mu \text{m}$ .

Experimental Study on the Subthreshold Swing of Silicon Nanowire Transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.

FinFET Mismatch in Subthreshold Region: Theory and Experiments

In this paper, we study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view. We propose a simple model that takes into account the effect of threshold voltage and subthreshold swing fluctuations and their correlation. For long-channel devices (longer than a critical length LC), characterized by a subthreshold swing close to the ideal value, the overall current mismatch is dominated by threshold voltage fluctuations and, therefore, is gate voltage independent. The subthreshold swing fluctuations give a negligible effect on the drain-current mismatch and are uncorrelated with the threshold voltage fluctuations. For short-channel devices (shorter than a critical length LC), characterized by a strong dependence of subthreshold swing on the channel length, the overall current mismatch presents an additional relevant contribution associated with the subthreshold swing fluctuations. This component depends on the gate voltage overdrive and is ascribed to the gate line edge roughness, resulting in a partial correlation between threshold voltage and subthreshold swing fluctuations.

An analytical (classical) subthreshold behavior model for symmetrical fully‐depleted SOI double‐gate MOSFET's

Two dimensional device‐physics‐based analytical models are developed for subthreshold behavior in fully‐depleted SOI double‐gate MOSFET's. An analytical solution of Poisson's 2‐D equation is employed to establish the design equation for the subthreshold behavior in the fully‐depleted SOI double‐gate MOSFET's. The concept of effective conducting path explains the silicon film thickness (tsi ), front and back oxide thickness (tox ) and doping density (NA ) unified dependence of subthreshold swing (S). Furthermore, along with the effective conducting path, the minimum channel potential is used to precisely predict the threshold voltage roll‐off of the SOI double‐gate MOSFET's. This analytical model not only gives physical insight into the fully‐depleted SOI double‐gate MOSFET's device physics, but also provides basic designing guidelines for fully‐depleted double‐gate MOSFET's.