Density Of Interface Trap States Research Articles

All in-situ GaSb MOS structures on GaAs (001): Growth, passivation and high-k oxides

The GaSb-on-GaAs growth was optimized for the fabrication of metal-oxide-semiconductor (MOS) capacitors (Caps) with low interface state trap density (Dit) using in-situ deposited amorphous silicon (a-Si) interface passivation layer (IPL) and high-k oxides. The best top surface with the average roughness Ra=0.37nm and with spiral type “step-flow” growth mode was observed in the GaSb structure with the initial 0.5μm grown at 410°C and the top 0.5μm grown at 485°C. N- and p-type GaSb MOSCaps with reasonable capacitance–voltage(C–V) characteristics at room temperature (RT) were demonstrated using all in-situ 0.5nm a-Si IPL and 10nm Al2O3+HfO2 or Al2O3. A-Si IPL was found essential for n-MOSCaps but not in the case of p-MOSCaps where comparable C–V characteristics with a similarly low Dit=1–2×1012cm−2eV−1were demonstrated without IPL.

Improvement of the GaSb/Al2O3 interface using a thin InAs surface layer

The highly reactive GaSb surface was passivated with a thin InAs layer to limit interface trap state density (Dit) at the III–V/high-k oxide interface. This InAs surface was subjected to various cleaning processes to effectively reduce native oxides before atomic layer deposition (ALD). Ammonium sulfide pre-cleaning and trimethylaluminum/water ALD were used in conjunction to provide a clean interface and annealing in forming gas (FG) at 350°C resulted in an optimized fabrication for n-GaSb/InAs/high-k gate stacks. Interface trap density, Dit≈2–3×1012cm−2eV−1 resided near the n-GaSb conductance band which was extracted and compared with three different methods. Conductance–voltage–frequency plots showed efficient Fermi level movement and a sub-threshold slope of 200mV/dec. A composite high-k oxide process was also developed using ALD of Al2O3 and HfO2 resulting in a Dit≈6–7×1012cm−2eV−1. Subjecting these samples to a higher (450°C) processing temperature results in increased oxidation and a thermally unstable interface. p-GaSb displayed very fast minority carrier generation/recombination likely due to a high density of bulk traps in GaSb.

Electrical characterization of poly(amide-imide) for application in organic field effect devices

The admittance spectra and current–voltage (I–V) characteristics are reported of metal–insulator–metal (MIM) and metal–insulator–semiconductor (MIS) capacitors employing cross-linked poly(amide–imide) (c-PAI) as the insulator and poly(3-hexylthiophene) (P3HT) as the active semiconductor. The capacitance of the MIM devices are constant in the frequency range from 10Hz to 100kHz, with tanδ values as low as 7×10−3 over most of the range. Except at the lowest voltages, the I–V characteristics are well-described by the Schottky equation for thermal emission of electrons from the electrodes into the insulator. The admittance spectra of the MIS devices displayed a classic Maxwell–Wagner frequency response from which the transverse bulk hole mobility was estimated to be ∼2×10−5cm2V−1s−1 or ∼5×10−8cm2V−1s−1 depending on whether or not the surface of the insulator had been treated with hexamethyldisilazane (HMDS) prior to deposition of the P3HT. From the maximum loss observed in admittance-voltage plots, the interface trap density was estimated to be ∼5×1010cm−2eV−1 or ∼9×1010cm−2eV−1 again depending whether or not the insulator was treated with HMDS. We conclude, therefore, that HMDS plays a useful role in promoting order in the P3HT film as well as reducing the density of interface trap states. Although interposing the P3HT layer between the insulator and the gold electrode degrades the insulating properties of the c-PAI, nevertheless, they remain sufficiently good for use in organic electronic devices.

Transfer characteristic of zinc nitride based thin film transistors

AbstractPolycrystalline zinc nitride (Zn3N2) thin films were prepared on quartz and aluminum tin oxide/indium tin oxide (ATO/ITO) and SiO2‐covered crystalline silicon by reactive pulsed laser ablation (PLD) of a metallic zinc target using a pulsed Nd:YAG laser, assisted by a 13.56 MHz radio‐frequency (RF) nitrogen plasma. The microstructural, optical and electrical properties of the as‐deposited films were studied by Scanning Electron Microscopy (SEM), X‐ray diffraction (XRD), low‐temperature photoluminescence (PL), optical transmittance, and field effect transistor I‐V measurements. SEM revealed a compact and crack‐free film surface. XRD study indicated that the Zn3N2 films deposited at 673 K substrate temperature were cubic, with lattice constant a = 0.97 nm and having no preferred orientation. PL spectra taken at 4.2 K show a 7‐9 meV wide exciton‐related peak at 3.59 eV. The optical absorption coefficient, estimated from the transmission spectra using Beer's law, was utilized to determine the optical band gap of the films. The Zn3N2 showed a direct band gap of ∼3.2 eV at room temperature. Transparent field effect transistor structures with a 200 nm thick Zn3N2 film as active channel layer exhibited non‐linear I–V transfer characteristics, which is typical of devices having a large density of interface trap states (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Enhanced performance and reliability of NILC-TFTs using FSG buffer layer

A new manufacturing method for Ni-metal-induced lateral crystallization thin film transistors (NILC-TFTs) using fluorine-silicate-glass (FSG) was proposed. In FSG-TFTs, fluorine ion was implanted into the buffer oxide layer to form FSG before NILC processes. It was found FSG-TFTs exhibit high field-effect mobility, low threshold voltage, low subthreshold slope, high ON/OFF current ratio, low trap state density, low interface trap state density, and good reliability compared with typical NILC-TFTs.

AlN/GaN HEMTs with high‐κ ALD HfO2 or Ta2O5 gate insulation

AbstractAlN/GaN Metal‐Insulator‐Semiconductor High Electron Mobility Transistors (HEMTs) have been grown and fabricated which utilize a 6 nm thick atomic layer deposited film of either Ta2O5 or HfO2 for gate insulation. Drain, transfer, and gate current characteristics are compared between both structures, showing a measurable difference in threshold voltage and transconductance. The cause is highlighted by the results of capacitance‐voltage analysis which showed 10 MHz dielectric constants of 8.7 and 11.7 for the HfO2 and Ta2O5 films, respectively. Furthermore, interface trap state density was extracted by Terman's method and compared between films. HEMT small signal frequency performance was representative of the different sub‐micron gate lengths. Consideration of the compared electrical results suggests that at this stage in ALD development, Ta2O5 appears better suited for gate insulation of AlN/GaN HEMTs. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Electrical Characterization of TbScO3/TiN Gate Stacks of MOS Capacitors and MOSFETs on Strained and Unstrained SOI

We investigated the electrical and structural properties of TbScO3 as an alternative gate dielectric. Rutherford backscattering spectrometry revealed a stoichiometric film while X-ray photo-electron spectroscopy indicated silicate formation at the interface. Capacitance-Voltage measurements resulted in well behaving C-V curves with no hysteresis and a low density of interface trap states in the range of 4x1011 (eVcm2)-1. Fully depleted (FD) SOI and sSOI MOSFETs fabricated with a full replacement gate process show a steep subthreshold slope down to 81 mV/dec and high Ion/Ioff ratios up to 108. Low field electron mobilities of 181 cm2/Vsec for SOI and 350 cm2/Vsec for sSOI, were extracted, which are comparable to MOSFETs with Hf based oxides. Gate induced drain leakage (GIDL) investigations indicate a trap assisted band to band tunneling.

The influences of surface treatment and gas annealing conditions on the inversion behaviors of the atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitor

The inversion behaviors of atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors are studied by various surface treatments and postdeposition annealing using different gases. By using the combination of wet sulfide and dry trimethyl aluminum surface treatment along with pure hydrogen annealing, a strong inversion capacitance-voltage (C-V) response is observed, indicating a remarkable reduction in interface trap state density (Dit) at lower half-part of In0.53Ga0.47As band gap. This low Dit was confirmed by the temperature independent C-V stretch-out and horizontal C-V curves. The x-ray photoelectron spectroscopy spectra further confirm the effectiveness of hydrogen annealing on the reduction of native oxides.

Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures

The effect of interface state trap density, D it , on the current–voltage characteristics of four recently proposed III–V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δ -doping below the channel, a buried channel design with δ -doping, and implant-free quantum-well HEMT-like structure with no δ -doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δ -doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.

Effect of interface state trap density on the performance of scaled surface channel In0.3Ga0.7 As MOSFETs

The effect of interface state trap density, Dit, on the ID-VG characteristics of scaled surface channel MOSFETs based on In0.3 Ga0.7 As channel has been investigated using drift-diffusion simulations. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current when these devices are scaled from a gate length of 65 nm to 35 nm, 25 nm and 18 nm. The distributions of interface states having high density tails that extend into the conduction band can significantly impact the subthreshold performance of the larger gate length device. Furthermore, the same distributions have smaller impact on the performance of shorter channel devices which were designed with smaller high-κ thickness.

Simple Extraction Method of Interface Trap Density in Thin-Film Transistors

A simple method to extract the density of interface trap states from polycrystalline-silicon thin-film transistors with a doped active layer is proposed. In this method, an equation describing the interface trap charge density as functions of the front- and back-side surface potentials is derived, taking into account the dopant concentration in the channel region. Using both the front-side surface potential determined by the low frequency capacitance method, and the back-side surface potential obtained by using a compact modeling technique where is analytically calculated as a function of instead of solving the Poisson equation numerically, is calculated by taking the derivative of with respect to without assuming any specific distribution of interface trap states in the bandgap. The validity of the extraction method is confirmed using a two-dimensional device simulator. In addition, the results of applying this method to a real device are presented.

Effect of interface state trap density on the characteristics of n-type, enhancement-mode, implant-free In 0.3Ga 0.7As MOSFETs

The effect of interface state trap density, D it, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In 0.3Ga 0.7As MOSFETs [1,2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D it distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In 0.3Ga 0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.

Interface Trap Density and Mobility Characterization of Silicon Carbide MOSFET Inversion Layers

Silicon Carbide (SiC) based metal oxide semiconductor field effect transistors (MOSFETs) were fabricated and characterized using gated hall measurements with different p-type substrate doping concentration (7.2X1016cm-3 and 2X1017 cm-3). An interface trap state density of 5X1013 cm-2eV-1 was observed nearly 0.1 eV above the conduction band edge leading to the conclusion that these states are present in the silicon dioxide rather than the interface. The Hall mobility of the MOSFETs decreased from 26.5 to 20 cm2/Vs as the doping was increased from 7.2X1016 to 2X1017cm-3. The decrease in mobility is primarily due to an increase in the surface electric field that causes an increase in surface roughness scattering. The inversion layer mobility when plotted as a function of average surface electric field is not independent of doping concentration as is the case in silicon MOSFETs because the dominant scattering mechanism is not phonon scattering.

Extraction of the Density of Interface Trap States in Thin-Film Transistors

In the present study, we propose a new extraction method for the density of interface trap states at the Si/SiO2 interface from thin-film transistors with doped active layers. In developing the proposed method, we derive an equation that describes the interface trap charge density as functions of the surface potentials. Whereas the front surface potential is obtained from the low-frequency CV characteristic, the back surface potential is calculated using the depletion approximation. We confirm the validity of the extraction method using a two-dimensional device simulator.

Extraction of the Density of Interface Trap States in Thin-Film Transistors

not Available.

PREPARATION AND CHARACTERIZATION OF HAFNIUM SILICATE DIELECTRIC LAYERS BY PHOTO-ASSISTED MOCVD USING MIXED PRECURSOR OF Hf(O-t-C4H9)4 AND Si(O-t-C4H9)4

ABSTRACT Hafnium silicate dielectric layers have been prepared by photo-assisted metal organic chemical vapor deposition (MOCVD) using mixed precursor of Hf(O-t-C4H9)4 and Si(O-t-C4H9)4. Deuterium lamp was used for ultraviolet irradiation source to enhance decomposition of mixed precursor. It was confirmed from X-ray photoelectron spectroscopy (XPS) measurement that hafnium silicate dielectric layers were deposited successfully. The hafnium silicate dielectric layers exhibited improved surface roughness (0.12∼ 0.17 nm) and thermal stability. Electrical characterizations revealed that accumulated capacitance, leakage current and interface trap state density were improved, and these improvements may be caused from effective decomposition of mixed precursor by ultraviolet irradiation.

Electrical properties in vanadyl-phthalocyanine-based metal-insulator-semiconductor devices

We investigated electrical properties of vanadyl phthalocyanine (VOPc) metal-insulator-semiconductor (MIS) devices by the measurement of capacitance and conductance, which were fabricated on ordered para-sexiphenyl (p-6P) layer by weak epitaxy growth method. The VOPc∕p-6P MIS diodes showed a negligible hysteresis effect at a gate voltage of ±20V and small hysteresis effect at a gate voltage of ±40V due to the low interface trap state density of about 1×1010eV−1cm−2. Furthermore, a high transition frequency of about 10kHz was also observed under their accumulation mode. The results indicated that VOPc was a promising material and was suitable to be applied in active matrix liquid crystal displays and organic logic circuits.

Defect Reduction Treatment for Plasma–Tetraethylorthosilicate–SiO2 by High-Pressure H2O Vapor Heat Treatment

Improvements in the electrical and structural properties of tetraethylorthosilicate (TEOS) SiO2 films fabricated by plasma-enhanced chemical vapor deposition (PECVD) method were investigated using high-pressure H2O vapor heat treatment. The density of interface trap states was reduced from 3.3×1012 (initial) to 5.1×1010 cm-2 eV-1 by 1.3×106 Pa H2O vapor heat treatment at 260°C for 9 h. The density of fixed charges was also reduced from 6.1×1011 to 1.3×1011 cm-2. The full width at half-maximum (FWHM) of the optical absorption band corresponding to vibration of Si–O–Si bonding was reduced from 82.9 to 78.1 cm-1. Narrowing in FWHM of the Si 2p core level peak measured by X-ray photoelectron spectroscopy (XPS) was also observed. The reduction in the FWHM probably results from improvement of the Si–O bonding network.

Surface Photovoltage Spectroscopy for the Investigation of Perovskite Oxide Interfaces

AbstractIn the present study, we comparatively investigate the distribution of electronic interface states of three different perovskite oxide interfaces, formed by epitaxial thin films of La0.7Sr0.3MnO3 (LSMO), La0.7Ca0.3MnO3 (LCMO), and La0.7Ce0.3MnO3 (LCeMO) on SrTiO3(100) substrates, in the as-prepared state as well as after an annealing procedure. We find that annealing significantly reduces the number and density of interface trap states. Two different experimental realizations of the surface photovoltage spectroscopy (SPS) technique were employed: an approach based on X-ray photoelectron spectroscopy (XPS), as well as a capacitive method. The advantages and limitations of both methods are critically discussed.

Influence of implantation energy on the electrical properties of ultrathin gate oxides grown on nitrogen implanted Si substrates

Metal–oxide–semiconductor tunnel diodes with gate oxides, in the range of 2.5–3.5 nm, grown either on 25 or 3 keV nitrogen-implanted Si substrates at (0.3 or 1) ×1015 cm−2 dose, respectively, are investigated. The dependence of N2+ ion implant energy on the electrical quality of the growing oxide layers is studied through capacitance, equivalent parallel conductance, and gate current measurements. Superior electrical characteristics in terms of interface state trap density, leakage current, and breakdown fields are found for oxides obtained through 3 keV nitrogen implants. These findings together with the full absence of any extended defect in the silicon substrate make the low-energy nitrogen implantation technique an attractive option for reproducible low-cost growth of nanometer-thick gate oxides.