Sigma-delta Research Articles

Enhancing the performance of 16384QAM based on delta-sigma modulation using geometric shaping in an IMDD system.

In this Letter, a new, to the best of our knowledge, geometric shaping method for an ultrahigh-order 16384-ary quadrature amplitude modulation (16384QAM) constellation based on the delta-sigma modulation technique is proposed. Based on the characteristics of delta-sigma modulation, the constellation was optimized to obtain greater constellation gain and improve the maximum performance of the system. Finally, the proposed scheme was demonstrated on an intensity-modulated direct detection (IMDD) system through a 25 km single-mode fiber transmission. On performing experiments, it was found that the suggested approach increases the receiver sensitivity of ultrahigh-order QAM communication systems based on delta-sigma modulation by around 0.5 dB and further enhances the error performance limit.

IoT-interfaced solid-contact ion-selective electrodes for cyber-monitoring of element- specific nutrient information in hydroponics

This study aims to monitor element-specific nutrient information during hydroponic cultivation by IoT-interfaced miniaturized ion sensors. Because of size, cost, and manufacturing advantages, solid-contact ion-selective electrodes (SCISEs) were fabricated as an ion sensor array and interfaced with wireless embedded-systems to construct an IoT nutrient sensor system (IoNSS) for the first time. The entire IoNSS framework was composed of (i) a nutrient solution sampling and sensing module with SCISEs controlled by an Arduino Due® microcontroller, (ii) a Wio Terminal® microcontroller for automated procedure setting, data recording, and wireless transmission, (iii) a private cloud server (a Network Attached Storage equipped with Node-RED® and MongoDB®) for data management, and (iv) MQTT webpage-based interactive interfaces. In experiments, we found that potentiometric signal resolution and noise of the Arduino-interfaced SCISEs were significantly improved and approached to instrumental DAQ-like quality by additional delta-sigma ADC (ADS1115®) chip conditioning. This facilitated cost-effective harvest of precise and high-quality IoT ion sensor data. Before on-site applications, each SCISE was two-point calibrated in multiple-ion solutions and was checked with the fixed interference method. The ion concentration measurements were also compared with those of commercial ISEs and ion chromatography. To test the system’s feasibility, the IoNSS was applied to cyber-monitoring of K+, NO3–, and NH4+ concentrations during two-week hydroponic cultivation of arugula (E. vesicaria) in an indoor plant factory (in Northern Taiwan) with a modified Cornell solution and an outdoor greenhouse (in Southern Taiwan) with a modified Yamasaki solution, respectively. It was demonstrated that the IoNSS was capable of real-time observation of the crop’s nitrate/ammonium utilization and nutrient solution’s EC-element dependency. Besides, the web interfaces successfully reported growing condition-dependent ion signals in a simultaneous and remote manner. To sum up, this work achieves novel cybermonitoring of element-specific nutrients by IoT-interfaced SCISEs and paves a promising way for intelligent hydroponic management.

One-bit quantization delta-sigma modulation-based autoencoder for power-efficient free-space communication.

This Letter proposes a novel, to the best of our knowledge, approach utilizing a delta-sigma modulation (DSM)-based 1-bit autoencoder (AE) for efficient encoding and decoding in various channel conditions. Simulation analysis demonstrates the AE's ability to mitigate noise by reducing a peak-to-average power ratio (PAPR) and enhancing an in-band power of the signals, particularly under low signal-to-noise ratios (SNRs). The AE-DSM achieves theoretical transmission performance even at SNRs below 6 dB. In a 40-m free-space link experiment, the AE-DSM exhibits an 8.4-dB lower bit error rate (BER) compared to 64QAM-DSM, enabling a transmission rate of 1.31 Gbps. Furthermore, the 1-bit AE-DSM significantly reduces power consumption in the receiving analog-to-digital converter (ADC), facilitates transmission at low SNRs, and effectively mitigates nonlinear effects. Consequently, the DSM-based AE holds immense potential for future mobile fronthaul links.

A Sigma-Delta Modulator with Single-Pole Double-Throw Analog Switch

In this paper, a high precision and high energy efficiency discrete-time switching capacitive 3-order Sigma-Delta modulator (SDM) is proposed. The SDM is applied to portable electroencephalograms (EEG) because of its little energy and good performance. The energy efficiency levels of the current mainstream modulator systems are analyzed and compared, and the CIFF modulator architecture which is most conducive to realizing high energy efficiency is selected. The single-loop CIFF structure is selected to give consideration to the accuracy and stability of the circuit. The circuit is implemented in a hierarchical structure, and a single-pole double-throw (SPDT) analog switch is adopted to overcome the difficulty of opening conventional CMOS analog switches at low supply voltages and the increase in threshold voltage Vth of NMOS devices due to the base bias effect. The proposed discrete-time Sigma delta ADC modulator is designed with SMIC 0.18um CMOS technology and achieves an SNDR of 101.6dB under a 1.8V power supply voltage and a signal bandwidth of 2kHz. The power consumption is 520uW and the significant bit (ENOB) is 16.58 bits.

A Reference Voltage Circuit Applied in High Precision Delta-Sigma ADC

A novel reference voltage circuit design which is applied in high-precision Delta-Sigma ADC is implemented. The proposed reference circuit exploits a high-gain class-AB OTA as the error amplifier, which improves the transient response characteristics, ensures loop stability, and does not increase additional power consumption. The design and simulation of the proposed reference voltage circuit are fabricated by SMIC.18 CMOS technology. The simulation results manifest that the temperature coefficient of the bandgap reference is 6.825 ppm/°C in the temperature range from -40°C to 125°C. The transient response of the proposed reference circuit takes about 13 ns to reach the precision demanded by the reference voltage. The Σ-Δ modulator with the designed reference voltage circuit applied has an effective number of bits (ENOB) of 18.1 bits, a signal-to-noise-ratio (SNR) of 111.2 dB, and a signal-to-noise-plus-distortion (SNDR) of 110.9 dB at 1MHz sampling frequency and 625 Hz input signal.

A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC

A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC

A 111dB-SNDR 20kHz-BW Delta-Sigma Modulator with Auto-Zeroing and Class-AB Amplifier

This paper describes the design of a high-precision audio Delta-Sigma modulator. To guarantee the modulator linearity and resolution with a limited oversampling rate (OSR), 4th-order 1-bit architecture is chosen. Auto-zeroing technique is used to reduce offset and low-frequency noise. To optimize power consumption, the switched-capacitor loop filter is implemented by feedforward structure with a passive adder and class-AB two-stage amplifiers. A clock generator with optimized non-overlapping pulse widths is designed to improve precision. Simulation results in 180nm CMOS show that with a 10.24MHz sampling rate, the presented modulator achieves 111dB signal-to-noise-and-distortion ratio (SNDR) at 20kHz bandwidth (BW) and consumes 17.9mW power under 3.3V supply, corresponding to an excellent figure-of-merit (FoM) of 171.5dB. Simulation results in process corners and temperatures show that the modulator is robust over variations.

Design Specification and Simulations of a Miller compensated Operational Amplifier with 75dB Gain

This paper presents a two-stage Miller compensated operational amplifier design using cadence 55nm CMOS technology. This circuit provides a single ended output due to mirror pole is implemented while the input of this operational amplifier is differential. A biasing circuit is also designed and attached with this amplifier. This operational amplifier provides a gain of 75.41dB while the phase margin is off 70o. The Gain bandwidth of this operational amplifier is 9.5MHz. The power consumption of this overall circuit including the biasing circuit is 154.69µW. The other performance parameters are also analyzed and provide in this paper. The mathematical calculation for the circuits is also presented. Due to medium power consumption and higher gain bandwidth this amplifier can be used in different data converters like Delta-Sigma ADC. Because the performance of this ADC is depending upon the higher Gain Bandwidth.

Digital Pre-Distortion Based on Delta Sigma Modulation Assisted Look-Up Table for Optical Transmission

Digital Pre-Distortion Based on Delta Sigma Modulation Assisted Look-Up Table for Optical Transmission

Analysis and design of a fourth-order ΣΔ ADC for MEMS digital gyroscope sensors

This paper presents a fourth-order sigma-delta (ΣΔ) ADC applied to a micro-electro-mechanical system (MEMS) gyroscope system. First, a system-level model of ΣΔ modulator containing non-ideal factors is established, and the optimal system performance of the ΣΔ modulator is determined by optimizing the feedforward path and the feedback coefficient of the feedback path. Then, the operational transconductance amplifier (OTA) with chopping technique and clock timing to control bias current in the first stage integrator of the circuit design is able to reduce not only the flicker noise of the modulator, but also reduce the system power consumption. Third, the design of other essential circuit modules is presented, and the circuit performance meets the requirements and low-power consumption is achieved. The designed ΣΔ ADC uses a 0.18 μm CMOS BCD process, with a ΣΔ modulator area of 0.64 mm2 and a digital filter area of 2.03 mm2. When the sampling frequency is 2 MHz and the signal bandwidth is 7.8 kHz, the experimental measurement results show that the proposed ΣΔ modulator with the fourth-order CIFF structure can achieve a signal-to-noise ratio (SNR) of 66.3 dB and an effective number of bits (ENOB) of 10.07 bits, with a dynamic range (DR) of 89 dB and a power consumption of 9 mW. The SNR of ΣΔ ADC after filtering is 63 dB, which meets the requirements of high DR and low-power consumption of MEMS digital gyroscope sensors.

Lipschitz-Free Spaces over Cantor Sets and Approximation Properties

Let K=2^mathbb {N} be the Cantor set, let mathcal {M} be the set of all metrics d on K that give its usual (product) topology, and equip mathcal {M} with the topology of uniform convergence, where the metrics are regarded as functions on K^2. We prove that the set of metrics din mathcal {M} for which the Lipschitz-free space mathcal {F}(K,d) has the metric approximation property is a residual F_{sigma delta } set in mathcal {M}, and that the set of metrics din mathcal {M} for which mathcal {F}(K,d) fails the approximation property is a dense meager set in mathcal {M}. This answers a question posed by G. Godefroy.

Simple and low-latency multipoint-to-point aggregation architecture using commercial optical transceivers for uplink fronthaul.

The increasing demand of real-time applications poses a huge challenge to building next-generation radio access network (NG-RAN) with higher stability and lower system complexity. Parallel signal detection (PSD), which aggregates signals of different intermediate frequencies (IFs) on different wavelengths with a single photodiode (PD), becomes a promising candidate for uplink mobile fronthaul with the advantage of low-latency. However, high requirements on the transmitters inhibit the large-scale deployment of radio units (RU). In this paper, we propose an economical, low-latency, multipoint-to-point (MP2P) uplink fronthaul architecture capable of aggregating four end-users with commercial 25G-class optical modules and a single PD. With delta-sigma modulation (DSM), commercial off-the-shelf optical modules can replace analog transmitters in traditional systems. As a demonstration, we aggregated 4 × 380.16-MHz 5 G new radio (NR) orthogonal frequency division multiplexing (OFDM) signals in an IF band with a fixed interval of 400 MHz over 20 km fiber with 4 users.

Design and Analysis of a Buck–Boost DC–DC Converter with Delta-Sigma Modulator Controller

This paper presents a low-ripple and high-efficiency buck–boost DC–DC converter with delta-sigma modulator controller that converts 1.8 V to 1.2 V and 3.3 V. A current and voltage closed-loop controller has been designed to achieve better performance simultaneously such as lower settling-time, steady-state error and over shoot and under shoot. The converter is started in the current controller mode initially, when the output voltage approaches the desired value, the power stage is controlled with the voltage controller mode. PI compensator and a third-order delta-sigma modulator are utilized in the voltage mode. Also, the closed-loop stability of the designed converter has been analyzed with Lyapunov method using converter nonlinear model. This work has been simulated in MATLAB-SIMULINK environment. The performance results show that the maximum efficiency of the closed-loop DC–DC converter is 90% at 5[Formula: see text]MHz switching frequency, and the output voltage ripple is 0.5% and 0.6% for the buck and boost modes, respectively. Also, the simulation results demonstrate the closed-loop stability of the converter in the presence of 10% load variation.

Sigma-Delta Modulation on a Three-Phase Four-Leg VSI to Eliminate the Common Mode Voltage and Comply With the Military Standards

This paper demonstrates sigma-delta pulse density modulation (PDM) without common mode voltage on a four-leg voltage source inverter designed as a grid-forming inverter. Using PDM ensures that switching updates occur simultaneously for all phases and sigma-delta modulation is the most advantageous PDM for this application. The converter does not produce common mode voltage in the switching frequency range, thus meeting the conducted electromagnetic interference limits in MIL-STD-461G without the need for a large common mode choke. Further, the proposed common mode elimination method does not degrade the output voltage power quality, which meets the requirements in MIL-STD-1399 section 300 part I for type 1 voltage. The practical implementation of the control system on a Field Programmable Gate Array (FPGA) is presented and compliance with the two military standards is demonstrated on a laboratory prototype built with SiC MOSFETs.

A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization

This article presents a nested delta-sigma modulator (DSM) structure, where an inner analog DSM is embedded in an outer analog-digital-hybrid DSM. The outer hybrid DSM is composed of the inner analog DSM, a digital filter, and a hysteresis-comparison MSB-pass quantizer. The internal signal swing of the inner analog DSM can be significantly suppressed by the outer DSM loop, thus achieving good power efficiency. Compared to conventional system-level signal swing optimization techniques, the proposed nested DSM does not suffer from residual signal error issues and distortion leakage and is more digital-friendly with great flexibility. Fabricated in a 180 nm CMOS, the prototype analog-to-digital converter (ADC), using the nested DSM structure with hysteresis-comparison MSB-pass quantization, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR) of 110 dB/109.2 dB/119.6 dBc/110.3 dB, respectively. It achieves a measured Schreier figure of merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{S}})$</tex-math> </inline-formula> of 183.5 dB, which is among the best FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{S}}$</tex-math> </inline-formula> of the state-of-the-arts.

Reduction of Spurious Switching in Direct Vector Quantized Space Vector Pulse Density Modulation Scheme for Multilevel Inverters

A generalized online switching scheme for multi-level inverter based on Direct Vector Quantized Space Vector Pulse Density Modulation (DVQSVPDM) suitable for adjustable speed drive is proposed in this article. The existing DVQSVPDM schemes have spurious switching as the voronoi region is determined from integrated error vector of Sigma Delta Modulator (SDM). This results in high Total Harmonic Distortion (THD) of Common Mode Voltage (CMV) at lower modulation index. In the proposed DVQSVPDM the nearest three space vectors to the reference vector forms the triangular voronoi region. The integrated error vector of SDM is quantized to its nearest space vector in the voronoi region to generate the switching vectors. This reduces spurious switching associated with DVQSVPDM schemes and improves the performance at lower modulation index by reducing THD of CMV. The proposed scheme works for all n-level inverter topologies and the computations required remain same irrespective of level of inverter. Redundant states of switching vectors are not considered for switching which results in the discontinuous nature of proposed scheme. The performance of proposed DVQSVPDM is compared with space vector based modulation schemes and third harmonic injected sine PWM scheme and the results are presented. The proposed scheme is experimentally validated for a 3hp open end winding induction motor fed with three-level inverters on both sides.

Design of High Performance Operational Transconductance Amplifier

Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all the transistors are in saturation regime. Furthermore, in an effort to reduce costs and integrate analog and digital circuits onto a single chip, the analog designer must often face the challenges using CMOS processes. This paper covers the design and implementation of a novel CMOS folded cascode OTA designed in 1m technology. Covered topic include current source and sinks, differential amplifier, compensation techniques, two stage compensated OTA and cascode OTA. Our design emphasis is on practical design where power consumption and speed are critical. The OTA has very low settling time and can be used for high speed applications, such Analog-to–Digital converters, high speed Sigma-delta ADC.

A Novel Displacement Sensor Based on a Frequency Delta-Sigma Modulator and its Application to a Stylus Surface Profiler

A novel displacement sensor was proposed based on a frequency delta-sigma modulator (FDSM) employing a microwave oscillator. To demonstrate basic operation, we fabricated a stylus surface profiler using a cylindrical cavity resonator, where one end of the cavity is replaced by a thin metal diaphragm with a stylus probe tip. Good surface profile was successfully obtained with this device. A 10 nm depth trench was clearly observed together with a 10 μm trench in a single scan without gain control. This result clearly demonstrates an extremely wide dynamic range of the FDSM displacement sensors.

Efficient Sigma-Delta Sensor Array Beamforming.

Nowadays, sensors with built-in sigma-delta modulators (ΣΔMs) are widely used in consumer, industrial, automotive, and medical applications, as they have become a cost-effective and convenient way to deliver data to digital processors. This is the case for micro-electro-mechanical system (MEMS), digital microphones that convert analog audio to a pulse-density modulated (PDM) bitstream. However, as the ΣΔMs output a PDM signal, sensors require either built-in or external high-order decimation filters to demodulate the PDM signal to a baseband multi-bit pulse-code modulated (PCM) signal. Because of this extra circuit requirement, the implementation of sensor array algorithms, such as beamforming in embedded systems (where the processing resources are critical) or in very large-scale integration (VLSI) circuits (where the power and area are crucial) becomes especially expensive as a large number of parallel decimation filters are required. This article proposes a novel architecture for beamforming algorithm implementation that fuses delay and decimation operations based on maximally flat (MAXFLAT) filters to make array processing more affordable. As proof of concept, we present an implementation example of a delay-and-sum (DAS) beamformer at given spatial and frequency requirements using this novel approach. Under these specifications, the proposed architecture requires 52% lower storage resources and 19% lower computational resources than the most efficient state-of-the-art architecture.

PDM-OFDM 1-bit DSM 1024QAM/4096QAM signals at W-band transmission over 4.6-km wireless distance.

In this Letter, we propose the application of delta-sigma modulation (DSM) higher-order quadrature amplitude modulation (QAM) technology in long-distance transmission of W-band wireless communication, and demonstrate, for the first time to the best of our knowledge, the wireless transmission of millimeter wave signals in the W-band based on 1-bit DSM quantization using polarization-division-multiplexed orthogonal frequency division multiplexing (PDM-OFDM) 1024QAM/4096QAM for 4.6 km. We successfully achieved a bit error rate (BER) of 40-Gbit/s PDM-OFDM 1024QAM and 48-Gbit/s PDM-OFDM 4096QAM after 4.6-km wireless transmission, both lower than the soft decision forward error correction (SD-FEC) of 4.2 × 10-2. To the best of our knowledge, this is the first time that up to 4096QAM signals have been quantized and transmitted based on 1-bit DSM in a 4.6-km-long distance W-band millimeter wave system.