Sigma-delta Analog-to-digital Converter Research Articles

A 2nd Order Delta-Sigma ADC for Pressure Sensor Interface

A second order delta-sigma analog-to-digital converter (ADC) including a bandgap reference, a bias circuit for sensor, and a digital filter for the interface of piezoresistive pressure sensor is presented. The proposed sensor interface circuit is designed to target a pressure range from 0 to 100 psi. The prototype sensor interface circuit is implemented in a 0.35 μm CMOS process. The single-loop, 1-bit, second-order delta-sigma ADC operates at OSR of 256 achieves 80.5 dB dynamic range (DR), 79.6 dB peak signal-to-noise ratio (SNR), and 74.4 dB peak signal-to-noise and distortion ratio (SNDR) over a signal bandwidth of 7.8 kHz with 3.3V supply while consuming 0.33mW including on-chip reference and bias current for sensor. (in Performance Summary: 0.95mW)

A 0.9-V switched-opamp-based delta—sigma ADC with dual cycle shift DWA

This paper presents a low-power high-precision switched-opamp(SO)-based delta—sigma (ΔΣ) analog-to-digital converter (ADC). The proposed SO design allows circuit operation at sub-1 V supply voltage, only needs to work in half of a clock cycle, and thus is suitable for low power applications. In addition, an opamp-sharing technique is applied to save on hardware overheads. Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique, mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones. The proposed ADC has been implemented in a standard 0.18 μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth. The power consumption is 58 μW for the modulator at 0.9 V supply voltage and 96 μW for the decimation filter, which translate to the figure-of-merit (FOM) of 35.4 fJ/step for the solo modulator, and 94 fJ/step for the whole system.

17 bit 4.35 mW 1 kHz Delta Sigma ADC and 256-to-1 multiplexer for remote handling instrumentation equipment

A radiation tolerant Delta-Sigma Analog-to-Digital Converter (ADC) and multiplexer is presented. The design features a 1.5V, 17 bit ADC consuming 4.35mW at a sample frequency of 1MHz. The ADC features a bandwidth of 1kHz and utilizes a Correlated Double Sampling technique (CDS) to remove offset and 1/f noise. The circuit maintains its 17 bit resolution upon a simulated radiation dose exceeding 1MGy and varying temperatures between 0°C and 85°C. Next a multiplexer is presented. It can multiplex 256 channels at a clock frequency of 128MHz or has a data throughput of 256MSample/s. In addition the bit period of the multiplexer varies less then 1.5% due to the influence of temperature or radiation, which proves the temperature and radiation tolerance.

Sensitivity Analysis of Continuous-Time $\Delta \Sigma$ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers

The increasing demand for integrating multiple wireless services in one multi-standard handset, exemplified by the software-defined radio (SDR) model, calls for digitizing wireless receivers in a quest for flexibility. Radio-frequency (RF) front-end and analog baseband filters need to be exchanged for digital processing at the expense of a highly challenging analog-to-digital converter (ADC) specifications. In this paper, the sensitivities of continuous-time (CT) delta-sigma (ΔΣ) ADCs, which are candidate architectures for multi-standard receivers and SDRs, to out-of-band (OOB) blockers at the ADC input are investigated. This analysis addresses the problems and performance limitations that can result from large OOB blockers appearing at the input of CT ΔΣ modulators in a digitized multi-standard receiver. Analysis and discussions given in different sections of the paper are verified by CT system-level simulations.

배터리 용량측정을 위한 고해상도 Integrating Sigma-Delta ADC 설계

최근 모바일 기기의 수요의 증가와 더불어 다양한 멀티미디어 기능을 요구함에 따라 배터리 사용시간이 줄어들고 있다. 이에 따라 배터리 사용시간을 늘이기 위한 여러 가지 방법들이 제안되고 있다. 이러한 방법을 구현하기 위해서는 배터리 상태를 정확히 알아야 하며, 이를 위한 고해상도 아날로그-디지털 변환기를 필요로 하게 된다. 기존의 integrating sigma-delta ADC의 경우, 초기화-시간 변환시간을 해상도로 변환을 하지 않는 단점이 있다. 이런 단점으로 인해 bit수에 해당되는 모든 디지털 값을 표현 할 수 없게 된다. 위와 같은 단점을 보완하기 위해 본 논문에서는 올림/내림 계수기를 사용함으로써 초기화-시간 변환시간을 해상도로 변환을 하지 않고도 bit수에 해상되는 모든 디지털 값을 표현 가능하게 하였다. 이로 인해 기존 변환기의 시뮬레이션 결과에 비해 향상된 SDNR을 보여주었다. 또한 휴대용 배터리 관리 시스템에 적합하도록 저전력으로 설계를 진행 하였으며, 0.35-um 공정으로 제작이 이루어졌다. Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

Multi-Band Digital-RF Receiver

A software radio receiver that can be programmed to operate in multiple wide frequency bands is required for many communication and intelligence applications. We have designed a variety of multi-band receivers, comprising a set of band-specific analog-to-digital converters (ADCs) for direct digitization of RF bands and a digital switch matrix for band selection, in two flavors: as a single superconductor integrated circuit chip and also as a multi-chip module. In addition to the ADCs and the switch, these include a 1:16 deserializer and output drivers to facilitate transport of the digitized RF data to room temperature electronics for further processing and analysis. In the single IC flavor, up to four bandpass delta-sigma ADCs minimizing quantization noise in their respective bands were integrated on the same chip and operated at clock rates up to 20 GHz. In the multi-chip module (MCM) implementation, a 1-cm × 1-cm universal active carrier was designed to accommodate any two 2.5-mm × 2.5-mm flipped chips, each containing a single ADC front-end. This standardized approach facilitates customization of two-band ADCs by selecting from a growing library of ADC front-ends, which currently cover bands ranging from HF (0-30 MHz) to Ka-band (20-21 GHz). These Multi-band MCMs and single chip ADC's were fabricated, assembled and tested.

A Dynamic Dither Gain Control Technique for Multi-Level Delta-Sigma DACs with Multi-Stage Second Order Dynamic Element Matching

A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10dB improvement of THD+N performance under -50dB amplitude input signal, compared to the case without the proposed technique.

A 2.5 V 109 dB DR ΔΣ ADC for Audio Application

Abstract— A 2.5 V feed-forward second-order delta-sigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analog-to-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 mm 2 and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply. Index Terms —Delta-sigma modulator, feed-forward, dynamic element matching, chopper stabilization I. I NTRODUCTION Recent advances of CMOS technology have enabled the high quality signal processing in the multi-media and communication systems and have resulted in a great demand for the high resolution analog-to-digital converters (ADCs). Among various ADC architectures, the delta-sigma ADC offers high dynamic range by using oversampling and noise shaping properties. Moreover, as it requires only simple and relatively high-tolerance analog components with fast and complex digital signal processing to achieve high resolution, it is very well-suited for the digital CMOS process. The theoretical signal-to-quantization noise ratio (SQNR) of the delta-sigma ADC is given by Eq. (1)

Implementation of delta—sigma analog‐to‐digital converter in LTPS process

Abstract— An on‐panel delta—sigma analog‐to‐digital converter (ADC) has been implemented and verified for 3‐μm low‐temperature polysilicon (LTPS) technology with two basic blocks: a delta—sigma modulator and a decimation filter. From the experimental results, the digital output from the delta—sigma modulator is correctly matched with the analog input voltage ratio such that the digital output can be converted into 8‐bit digital code successfully under a supply voltage of 10 V from the decimation filter. The implemented on‐panel delta—sigma ADC can be used for the application of temperature‐to‐digital converter on glass substrate.

Systematic design of wideband ΔΣ modulators for WiFi/WiMAX receivers

Modern multi-standard receivers in deep-submicron technologies pose significant design challenges on the analog baseband. Moving this analog filtering to the digital domain simplifies the design, yielding a process-scalable implementation. However, analog-to-digital converter (ADC) specifications now become more stringent and must be obtained by comprehending the standard and the system. Assuming a receiver NF of 5.96 dB and SNR degradation of 0.36 dB by the ADC, the proposed dual-mode WiFi/WiMAX receiver attains an input sensitivity of ?74 dBm (20 MHz channel bandwidth). To accommodate the high dynamic range and the anti-alias rejection needed for the system, a Delta-Sigma (ΔΣ) ADC is proposed. Single-loop and Multi-Stage Noise-Shaping (MASH) architectures that achieve a SNR of 69 dB at a low oversampling ratio (OSR) of 8 for a conversion bandwidth of 40 MHz (108 Mbps, OFDM) are investigated at system level. Based on thermal noise, harmonic distortion, and power tradeoffs, a ΔΣ ADC design that meets the design specifications is presented.

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma–delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2–2 multi-bit cascaded sigma–delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC. The modulator has been implemented by a 0.18 μm CMOS process and operates at a single 1.8 V supply voltage. Experimental results show that for a 1.25 MHz @ −6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.

Simulative Evaluation of SNR in Asynchronous Sigma-Delta ADC

This paper shows the difference between the SNR level for classical synchronous analog-to-digital converters (ADC) and asynchronous Sigma-Delta analog-to-digital converters (ASD-ADC). Simulative evaluation shows that conversion quality for ASD-ADC is 2 bit worse than for classical synchronous ADCs. The reason of such difference is at first the nonlinearity of ASD-ADC sampling block (ASDM) and at second quantization noise bigger than in classical ADCs. The quantization noise is caused by the need of two independent pulse edges time position measurements. The SNR is evaluated for three stochastic models of input signals: Gauss, uniform, sinusoidal.

An Asynchronous Sigma Delta Analog to Digital Converter for Broadband Wireless Receiver with Adaptive Digital Filtering Technique

This paper focuses on the circuit design techniques for an asynchronous sigma delta Analog to Digital Converter (ADC). The key advantage of this ADC approach is the potential for dynamic range to improve with the evolution of CMOS fabrication process. In contrast, conventional synchronous sigma delta ADC does not enjoy the benefit of improved dynamic range and lower power consumption from the scaling of CMOS fabrication process. The asynchronous approach has already been proposed in the past, but no actual circuits have been designed and published. As a case study, the asynchronous sigma delta ADC is designed according to Worldwide Interoperability for Microwave Access (WiMAX) communication standard. Novel circuit elements, such as integrator, hysteresis comparator and the time to digital converter (TDC), are proposed in this paper for the asynchronous sigma delta ADC. The overall power consumption of this ADC is just 9.4 mW, which is one of the lowest compared to the existing synchronous sigma delta designs.

Special Issue on Signal Processing for Software Defined Radio Handsets

The ultimate objective of Software Defined Radio (SDR) is to replace the entire analog signal processing in the wireless transceivers with digital signal processing. This will provide the flexibility, through reconfiguration or reprogramming, to enable the transceivers to work with different air-interfaces standards using a single generic hardware platform. Most of the research in SDR to date has been focused on base stations, which do not have as tight constraints in size and power consumption as handsets. However, in order to realize the promise of integrated services and global roaming capabilities, the design and development of a multi-standard SDR handset with dynamic reconfigurability is crucial. The size and power constraints imposed by handsets with limited resources pose a major design challenge. This special issue brings together 11 papers that address various aspects of this challenge from the perspectives of wireless systems, computing architectures, embedded systems and signal processing. The most important part of an SDR transceiver is the wideband analog-to-digital converter (ADC) that converts the radio frequency signal received by the antenna into digital form for further processing. The first paper, “A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications” by Jose et. al. proposed a cascaded reconfigurable sigma-delta modulator that is able to work with three different communication standards. This design, implemented in 0.18 μm CMOS technology, exhibits excellent signal-to-noise plus distortion ratios and has reduced power consumption compared to conventional designs. After ADC, the digitized received signal will need to be separated into signals within the various bands specified by the communication standard. This is performed by the channelizer which has the highest computational requirements of the whole SDR system. The second paper, by Panicker et al., reviews the state-of-the-art filter bank channelizer techniques with low power and dynamic reconfigurability properties. The design of reconfigurable devices can be optimized using the methodology of parametrization which bring together the common aspects of a myriad number of wireless standards into a single processing procedure. In this way, the implementation of the multi-standard SDR will be greatly simplified. “Promising technique of parametrisation for reconfigurable radio, the Common Operators Technique: fundamentals and examples” by Alaus et al. presents the common operator technique for parametrization which is less standards dependent than the more conventional Common Function technique. The direct digitization of the radio frequency (RF) signal requires very high speed ADCs which is not readily available using current technology. Therefore, current SDR implementations typically down-converts the RF A. P. Vinod (*) School of Computer Engineering, Nanyang Technological University, Nanyang, Singapore e-mail: asvinod@ntu.edu.sg

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

To alleviate the image-rejection requirements of the front-end filters and the feedback digital-to-analog converter (DAC) matching requirements, an oversampling complex discrete-time (DT) DeltaSigma analog-to-digital converter (ADC) with a signal-transfer function that achieves significant filtering of interfering signals is proposed. With a filtering signal transfer function (STF) and stopband attenuation greater than 30 dB, the DeltaSigma modulator reduces the intermodulation of the desired signal and the interfering signals at the input of a quantizer, and also avoids feedback of high-frequency interfering signals at the input of the modulator. This filtering of the interfering signals reduces sensitivity to DAC nonlinearities. The reported DT complex DeltaSigma ADC is intended for digital television (DTV) receiver applications. With a maximum intended sampling frequency of 128 MHz and an oversampling ratio of 16, the ADC has been designed to support a maximum DTV signal bandwidth of 8 MHz. The IC achieved a 70.9-dB signal-to-noise-and-distortion ratio over a 6-MHz band centered around 3 MHz. The image-rejection ratio of the DeltaSigma ADC was measured to be greater than 65 dB. The fabricated chip consumes 122.4 mW and occupies a silicon area of 2.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Wideband Sigma-Delta Modulator With Cross-Coupled Two-Paths

The performance of a sigma-delta analog-to-digital converter (ADC) critically depends on one or more of the main three parameters: over-sampling ratio, the order of the modulators, and the number of bits used. Increasing each one of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a method to obtain high order noise shaping with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -path architectures that are based on first-order or second-order modulators. The desired noise transfer function (NTF) is obtained by suitable cross-coupling paths. The method was applied to a two-path first-order modulator for obtaining a second-order noise shaping. The performances of the proposed sigma-delta ADC were verified at the behavioral and transistor level implemented in 90-nm CMOS technology.

A Theoretical Study of the Quantization Noise in Split Delta–Sigma ADCs

A theoretical analysis of the statistics of the quantization noise in split delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is presented. Sufficient conditions are derived that ensure that the quantization noise components of the constituent DeltaSigma modulators are asymptotically independent of each other, the input, delayed versions of themselves, and uniformly distributed. The application of the conditions is illustrated for two useful classes of split DeltaSigma ADCs.

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

Asynchronous Sigma-Delta analog-to digital converter based on the charge pump integrator

The concept of the asynchronous Sigma-Delta analog-to-digital converter (ASD-ADC) based on the charge pump integrator is discussed in the paper. A two-level conversion scheme is utilized. The first level is accomplished by amplitude-to-pulse-width mapping in the asynchronous Sigma-Delta modulator. The other level consists in the time-to-digital conversion. The ASD-ADC belongs to a class of mean value converters since the digital outputs correspond to the mean values of the input signal in time windows of varying width. The configurations of the charge pump modulator either with bipolar, or with unipolar controlled current sources are presented. The design of the charge-pump-based modulator model using classical solutions of bipolar technology is exemplified. The input/output simulation results of the designed asynchronous Sigma-Delta modulator (ASDM) are reported. Next, the design of the time-to-digital converter, the analysis of the quantization error, and two concepts of the converter digital output interface are presented. The comparison of the minimum transmission bit rate of the serial output port(s) for both concepts is carried out. Finally, the procedure of evaluation of the ASD-ADC key design parameters for speech signal supporting a possible original input signal recovery is exemplified.

A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely controlled by a novel reference stage. A new dynamic element matching algorithm, based on split-set data-weighted averaging (SDWA), is used to improve the dynamic range and to reduce the nonlinearity caused by mismatches in the multibit DAC.