Delayed Least Mean Square Research Articles

High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE

This brief presents a high-performance VLSI architecture of delayed least mean square (DLMS) adaptive filter for fast-convergence and low-mean square error (MSE) using distributed arithmetic (DA). The proposed design estimates response against the adaptation delays using a parallel predictive adder tree followed by a shift accumulate (SA) unit. An efficient quantization scheme with two bits of scaled error signal is also suggested. Single SA unit for multiple DA bases is used to reduce the number of adders and registers. Simulation and synthesis results show that the proposed design for 32 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order provides 19.72% lesser area, 25.51% lesser power, lesser 28.89% MSE and 59.91% lesser MSE/area over the best existing design.

A Novel Low-Power High-Precision Implementation for Sign–Magnitude DLMS Adaptive Filters

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities.

Design and implementation of HF signal receiving and processing module based on FPGA

This article designs and implements a receiving processing module based on the Xilinx ZCU102 evaluation board for the signal waveform defined in Appendix C of MIL-STD-188-110C. The focus is on the digital down-conversion, synchronization capture, and adaptive equalization algorithm for this signal processing module. Compare and design two adaptive algorithms, LMS (Least Mean Square) and DLMS (Delayed Least Mean Square). LMS algorithm has better convergence effect than DLMS algorithm, and the calculation efficiency is lower than the DLMS algorithm based on the structure of the systolic array. The signal waveform is tested under CCIR (International Radio Consultative Committee) HF (High Frequency) channel. The experimental results show that the receiving processing module has good feasibility for signals under medium HF channels.

Design of an Optimized Twin Mode Reconfigurable Adaptive FIR Filter Architecture for Speech Signal Processing

Reconfigurability, low complexity and low power are the key requirements of FIR filters employed in multi-standard wireless communication systems. Digital Filters are used to filter the audio data stream and increase the reliability of speech signal. Therefore, it is imperative to design an area optimized and low power based reconfigurable FIR filter architectures. The reconfigurable architecture designed in this research is capable of achieving lower adaptation-delay and area-delay-power efficient implementation of a Delayed Least Mean Square (DLMS) adaptive filter with reversible logic gates. The Optimized Adaptive Reconfigurable Adaptive Reconfigurable (OAR) FIR filter architectures are proposed. The optimized architectures are implemented across the combinational blocks by reducing the pipeline delays, sampling period, energy consumption and area, to increase the Power-Delay Product (PDP) and Energy Per Sample (EPS).The noisy speech signals are used for verifying the efficiency of the proposed architectures. The efficiency of the architecture is verified by implementing the proposed scheme in signal corrupted by various real-time noises at different Signal to Noise Ratios (SNRs).

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

In this paper, a fixed-point finite impulse response adaptive filter is proposed using approximate distributed arithmetic (DA) circuits. In this design, the radix-8 Booth algorithm is used to reduce the number of partial products in the DA architecture, although no multiplication is explicitly performed. In addition, the partial products are approximately generated by truncating the input data with an error compensation. To further reduce hardware costs, an approximate Wallace tree is considered for the accumulation of partial products. As a result, the delay, area, and power consumption of the proposed design are significantly reduced. The application of system identification using a 48-tap bandpass filter and a 103-tap high-pass filter shows that the approximate design achieves a similar accuracy as its accurate counterpart. Compared with the state-of-the-art adaptive filter using bit-level pruning in the adder tree (referred to as the delayed least mean square (DLMS) design), it has a lower steady-state mean squared error and a smaller normalized misalignment. Synthesis results show that the proposed design attains on average a 55% reduction in energy per operation (EPO) and a 3.2× throughput per area compared with an accurate design. Moreover, the proposed design achieves 45%-61% lower EPO compared with the DLMS design. A saccadic system using the proposed approximate adaptive filterbased cerebellar model achieves a similar retinal slip as using an accurate filter. These results are promising for the large-scale integration of approximate circuits into high-performance and energy-efficient systems for error-resilient applications.

Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel

Many pipelined adaptive signal processing systems are subject to a tradeoff between throughput and signal processing performance incurred by the pipelined adaptation feedback loops. In the conventional synchronous design regime, such throughput/performance tradeoff is typically fixed since the pipeline depth is usually determined in the design phase and remains unchanged in the run time. Nevertheless, in many real-life scenarios, the overall system performance can be potentially improved if we can run-time dynamically configure this tradeoff. With this motivation, we propose to apply self-timed pipeline, an alternative to synchronous pipeline, to implement the pipelined adaptive signal processing systems, in which the pipeline depth can be dynamically changed to realize run-time configurable throughput/performance tradeoffs. Based on a well-known high speed self-timed pipeline style, we developed architecture and circuit level design techniques to implement the self-timed pipelined adaptation feedback loop with configurable pipeline depth. We demonstrate the proposed design approach using a delayed least mean square (DLMS) adaptive equalizer for magnetic recording read channel. The data transfer rate in hard disk varies as the read head moves among tracks with different distance from the center of the disk platter. By adjusting the pipeline depth on-the-fly, the DLMS equalizer can dynamically track the best equalization performance allowed by the varying data transfer rates. Simulation result shows a significant performance improvement compared with its synchronous counterpart.

Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

A new realization of 2-D adaptive separable-denominator state-space filters based on DLMS algorithm suitable for parallel processing

In the application of 2-D adaptive filters, a large amount of data must be processed and real-time processing is often required. In this paper, a new parallel-form realization of 2-D adaptive separable-denominator state-space filters suitable for high-speed processing is proposed. First, the 2-D local state-space model suitable for parallel processing is introduced. Next, the adaptive algorithm for this model is developed. This algorithm is based on the delayed least mean square (DLMS) method. In addition, the computation time required for the update of the coefficients is investigated. Finally, the proposed technique is applied to the design of 2-D digital filters in the spatial domain.

Leaky Delayed LMS Algorithm: Stochastic Analysis for Gaussian Data and Delay Modeling Error

This paper presents a stochastic analysis of the delayed least-mean-square (DLMS) adaptive algorithm with leakage. This analysis is obtained taking into account that mismatches between the system delay and its estimate may occur. Such an approach is not considered in previous models. In addition, it is shown that the introduction of a leakage factor into the adaptive algorithm keeps the adaptive algorithm stable under an imperfect delay estimate condition. Recursive difference equations for the first and second moments of the adaptive filter weights are derived. An expression for the critical value of the step size is also determined. Results of Monte Carlo simulations present excellent agreement with the proposed model for both white and colored Gaussian inputs.

Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.

A new architecture for implementing pipelined FIR ADF based on classification of coefficients

In this paper, we propose a new method for implementing pipelined finite-impulse response (FIR) adaptive digital filter (ADF), with an aim of reducing the maximum delay of the filtering portion of conventional delayed least mean square (DLMS) pipelined ADF. We achieve a filtering section with a maximum delay of one by simplifying a pre-upsampled and a post-downsampled FIR filter using the concept of classification of coefficients. This reduction is independent of the order of the filter, which is an advantage when the order of the filter is very large, and as a result the method can also be applied to infinite impulse response (IIR) filters. Furthermore, when the proposed method is compared with the transpose ADF, which has a filtering section with zero delay, it is realized that it significantly reduces the maximum delay associated with updating the coefficients of FIR ADF. The effect of this is that, the proposed method exhibits a higher convergence speed in comparison to the transpose FIR ADF.

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation.

Pipelined DFE architectures using delayed coefficient adaptation

In this paper the delayed least-mean-square (DLMS) algorithm is proposed for training a transversal filter-based decision feedback equalizer (DFE). Delays in the filter coefficient update process are used to pipeline the DFE, thereby increasing the throughput rate, for a given speed of hardware. The filter structures selected for the feedforward and feedback section of the DFE facilitate the use of a shared error signal, thereby reducing communication costs. The new resulting structure is highly modular and is very suitable for very large scale integration (VLSI) implementation. A pipelined form for the normalized least-mean-square algorithm (NMLS) is also obtained which removes the dependency of the convergence speed on the input signal power. The convergence and residual mean-square error characteristics of the different pipelined filters are compared.

Pipelined adaptive filters based on delayed LMS algorithm

The delayed least mean square (DLMS) algorithm has been known as a possible pipelined algorithm. DLMS can be considered as a special case of pipelined LMS (PIPLMS), but it has a faster convergence speed than PIPLMS. For the conventional pipelined architecture based on DLMS, in order to keep the same input signal clock rate, independent of the filter order, a one-tap filter is put into one cell. However, as the filter order increases, the convergence behavior degrades, latency increases, and the tracking capability deteriorates. This paper proposes an architecture, in which one cell includes a multitap filter. Thus, the convergence behavior and latency can be improved, and its effectiveness has been confirmed by computer simulation. In addition, computations within a cell can be scheduled, and the decrease of the signal clock rate can be restrained. It is demonstrated that about half the amount of hardware can be saved with this proposed method. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(12): 82-90, 1997

Bit-serial VLSI implementation of delayed LMS adaptive FIR filters

The delayed least-mean-square (DLMS) algorithm is useful for adaptive finite impulse response (FIR) filtering applications where high throughput rates are required. In the paper, a bit-serial bit-level systolic array based on new schemes for multiplication and inner-product computation is presented to implement DLMS adaptive N-tap FIR filters. The architecture is highly regular, modular, and thus well-suited to VLSI implementation. It has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N/2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance under proper selection of the step size. Based on a conservative design technique of static complementary metal oxide semiconductor (CMOS) logic, it is shown that the proposed system can be realized in a single chip for most practical applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The LMS algorithm with delayed coefficient adaptation

The behavior of the delayed least-mean-square (DLMS) algorithm is studied. It is found that the step size in the coefficient update plays a key role in the convergence and stability of the algorithm. An upper bound for the step size is derived that ensures the stability of the DLMS. The relationship between the step size and the convergence speed, and the effect of the delay on the convergence speed, are also studied. The analytical results are supported by computer simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>