Delay Tradeoff Research Articles

Walking on two legs: Joint service placement and computation configuration for provisioning containerized services at edges

With the development of edge computing and container virtualization, provisioning containerized services at network edges is proposed for high responsiveness and low wide area network (WAN) traffic. However, realizing its full potential faces multiple challenges. First, due to containers’ fine-grained computation resource isolation, finely configuring services’ computation resource requirements is needed, especially for resource-constrained edge nodes. Second, due to edges’ heterogeneity and services’ diversity, system performance highly depends on which edge node to place each service. Third, as the main metric of quality of service, service response time involves the computing-network delay tradeoff and urges to optimize the decisions jointly. Prior works on edge-enabled service placement either ignore computation resource isolation and configuration, or assume computation resource configuration is given manually. To fill this gap, this paper investigates the joint service placement and computation configuration problem for provisioning containerized services at edges. Then based on the convex and submodular optimization techniques, we propose a two-stage greedy and local-search combined algorithm, TeLa for short. Rigorous theoretical analyses demonstrate that TeLa is a polynomial-time algorithm with performance guarantees. Finally, we implement twelve containerized services and an edge computing prototype to realistically evaluate TeLa. The results confirm TeLa’s empirical superiority over state-of-the-art algorithms, in terms of 39% on average reduction on the weighted sum of service response time and WAN traffic.

Computation Offloading for Energy and Delay Trade-Offs With Traffic Flow Prediction in Edge Computing-Enabled IoV

An unprecedented prosperity in artificial intelligence promotes the development of Internet of Vehicles (IoV). Assisted by edge computing, vehicles enable to offload data to edge servers in close proximity to users for processing, thus making up for the shortage of local computing resources. However, due to the uneven space-time distribution of traffic flow, edge servers of a certain road segment may be overwhelmed by the surge of service requests. Furthermore, IoV system will incur significant additional energy consumption and time delay because of the absence of a proper computation offloading scheme between edge servers. To cope with above challenges, a computing offloading method for energy and delay trade-offs with traffic flow prediction in edge computing-enabled IoV is proposed. We first design the graph weighted convolution network (GWCN) that can fully excavate the connectivity and distance relation information between road segments to conduct traffic flow prediction. The short-term prediction results are utilized as the basis for adjusting the resource allocation of edge resources in different regions. Then, a computation offloading method driven by deep deterministic policy gradient (DDPG) is leveraged to obtain an optimal computation offloading scheme for edge servers. Finally, extensive comparative experiments demonstrate the low prediction error of GWCN and superior performance of DDPG-driven method in reducing total time delay and energy consumption.

Optimization of Delay Using Killer Whale Algorithm (KWA) on NB-IoT

Abstract: NB-IoT is designed to connect IoT devices with low-power, wide-area coverage and efficient costs. Ensuring optimal data transmission delay is a challenge in NB-IoT implementation. Inadequate coverage can hinder IoT adoption. Optimization balances energy saving and delay trade-off. The Killer Whale Algorithm (KWA) optimizes delay by adjusting repetition variables. KWA addresses dimensions, variable limits. Applying KWA in NB-IoT optimizes transmission, enhancing QoS. Optimizing delay involves reducing latency in uplink data transmission using repetition variables. This study applies KWA to optimize NB-IoT delay. Analysis in Table 4 shows non-linear repetition-distance correlation. Interestingly, delay outcomes exhibit a contrasting relationship. Still, delay remains advantageous, remaining under 1 second even at 10 km, specifically 9.2674 ms (0.0092674 seconds). This thesis aims to optimize delay in NB-IoT network transmission using the Killer Whale Algorithm (KWA), crucial for modern communication networks and IoT applications. Leveraging KWA, the research identifies solutions to reduce transmission delay, enhancing efficiency and meeting IoT communication demands for speed and timeliness

Optimal Energy and Delay Tradeoff in UAV-Enabled Wireless Sensor Networks

Unmanned aerial vehicles (UAVs) are promising in large-area data collection due to their flexibility and easy maintenance. In this work, we study a UAV-enabled wireless sensor network (WSN), where K UAVs are dispatched to collect a certain amount of data from each node on the ground. Most existing works assume that the flight energy is either distance-related or duration-related, which may not suit the practical scenario. Given the practical speed-related flight energy model, we focus on deriving the optimal energy and delay tradeoff for the K UAVs such that each node can successfully upload a certain amount of data to one of the K UAVs. Intuitively, the higher flight speed of the UAV results in the shorter completion time of the data collection task, which may however cause the higher flight energy consumption of UAVs during the task. Specifically, we first model the total energy consumption of the UAV during the flight for collecting data within the WSN and then design the flight speed as well as the flight trajectory of each UAV for achieving different Pareto-optimal tradeoffs between the maximum single-UAV energy consumption among all UAVs and the task completion time. To achieve this goal, we propose a novel multi-objective ant colony optimization framework based on the adaptive coordinate method (MOACO-ACM). Firstly, the adaptive coordinate method is developed to decide the nodes visited by each of the K UAVs, respectively. Secondly, the ant colony algorithm is incorporated to optimize the visiting order of nodes for each UAV. Finally, we discuss the impact of UAVs’ speeds scheduling on the tradeoff between the task completion time and the maximum single-UAV energy consumption among all UAVs. Extensive simulations validate the effectiveness of our designed algorithm and further highlight the importance of UAVs’ flight speeds in achieving both energy-efficient and time-efficient data collection.

Service Delay Minimization for Federated Learning Over Mobile Devices

Federated learning (FL) over mobile devices has fostered numerous intriguing applications/services, many of which are delay-sensitive. In this paper, we propose a service delay efficient FL (SDEFL) scheme over mobile devices. Unlike traditional communication efficient FL, which regards wireless communications as the bottleneck, we find that under many situations, the local computing delay is comparable to the communication delay during the FL training process, given the development of high-speed wireless transmission techniques. Thus, the service delay in FL should be computing delay + communication delay over training rounds. To minimize the service delay of FL, simply reducing local computing/communication delay independently is not enough. The delay trade-off between local computing and wireless communications must be considered. Besides, we empirically study the impacts of local computing control and compression strategies (i.e., the number of local updates, weight quantization, and gradient quantization) on computing, communication and service delays. Based on those trade-off observation and empirical studies, we develop an optimization scheme to minimize the service delay of FL over heterogeneous devices. We establish testbeds and conduct extensive emulations/experiments to verify our theoretical analysis. The results show that SDEFL reduces notable service delay with a small accuracy drop compared to peer designs.

Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models

While high-level synthesis (HLS) tools offer faster design of hardware accelerators with different area versus delay tradeoffs, HLS-based delay estimates often deviate significantly from results obtained from ASIC logic synthesis (LS) tools. Current HLS tools rely on simple additive delay models which fail to capture the downstream optimizations performed during LS and technology mapping. Inaccurate delay estimates prevent fast and accurate design-space exploration without performing time-consuming LS tasks. In this work, we exploit different machine learning models which automatically learn to map the different downstream optimizations onto the HLS critical paths. In particular, we compare graph-based and nongraph-based learning models to investigate their efficacy, devise hybrid models to get the best of the both worlds. To carry out our learning-assisted methodology, we create a dataset of different HLS benchmarks and develop an automated framework, which extends a commercial HLS toolchain, to extract essential information from LS critical path and automatically matches this information to HLS path. This is a nontrivial task to perform manually due to difference in level of abstractions. Finally, we train the proposed hybrid models through inductive learning and integrate them in the commercial HLS toolchain to improve delay prediction accuracy. Experimental results demonstrate significant improvements in delay estimation accuracy across a wide variety of benchmark designs. We demonstrate that the graph-based models can infer essential structural features from the input design, while incorporating them into traditional nongraph-based models can significantly improve the model accuracy. Such “hybrid” models can improve delay prediction accuracy by 93% compared to simple additive models and provide <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$175\times $ </tex-math></inline-formula> speedup compared to LS. Furthermore, we discuss key insights from our experiments, identifying the influence of different HLS features on model performance.

Proficient matrix codes for error detection and correctionin 8-port network on chip routers

This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

Energy and delay trade-offs of end-to-end vehicular communications using a hyperfractal urban modelling

We characterise trade-offs between the end-to-end communication delay and the energy in urban vehicular communications with infrastructure assistance. Our study exploits the self-similarity of the location of communication entities in cities by modelling them with a hyperfractal model which characterises the distribution of mobile nodes and relay nodes by a fractal dimension dF and dr, both larger than the dimension of the embedded map. We compute theoretical bounds for the end-to-end communication hop count considering two different energy-minimising goals: either total accumulated energy or maximum energy per node. Let δ > 1 be the attenuation factor in the street, we prove that when we aim to a total energy cost of order n(1−δ)(1−α), the hop count for an end-to-end transmission is of order $n^{1-\alpha /(d_{F}-1)}$ , with α < 1 is a tunable parameter. This proves that for both goals, the energy decreases as we allow choosing routing paths of higher length. The asymptotic limit of the energy becomes significantly small when the number of nodes becomes asymptotically large. A lower bound on the network throughput capacity with constraints on path energy is also given. We show that our model fits real deployments where open data sets are available. The results are confirmed through simulations using different fractal dimensions in a Matlab simulator.

Managing Outpatient Service with Strategic Walk-ins

Outpatient care providers usually allow patients to access service via scheduling appointments or direct walk-in. Patients choose strategically between these two access channels (and otherwise balking) based on the trade-off of appointment delay and in-clinic waiting. How to manage outpatient care with such dual access channels, taking into account patient strategic choice behavior, is a challenge faced by providers. We study three operational levers to address this management challenge: service capacity allocation between these two channels, appointment delay information revelation via the choice and design of online scheduling systems, and a walk-in triage system that restricts the use of walk-in hours only for acute care. By studying a stylized queueing model, we find that neither a real-time online scheduling system (which offers instant access to appointment delay information at time of booking) nor an asynchronous online system (which does not directly provide delay information) can be universally more efficient. Although real-time systems appear more popular in practice, asynchronous systems sometimes can result in higher operational efficiency. Under the provider’s optimal capacity allocation, which scheduling system is more efficient hinges on two key factors: the patient demand–provider capacity relationship and patient willingness to wait. For the walk-in triage system, we find that it may or may not be beneficial to adopt; the provider’s own cost trade-off between lost demand and overtime work is the key determinant. Our research highlights that there is no one-size-fits-all model for outpatient care management, and the best use of operational levers critically depends on the practice environment. This paper was accepted by Jayashankar Swaminathan, operations management. Funding: S. Wang’s work was supported in part by the National Natural Science Foundation of China [Grants 72001220 and 71931008]. Supplemental Material: The online appendix is available at https://doi.org/10.1287/mnsc.2023.4676 .

A PVT tolerant latch in a 90-nm CMOS and performances under AC noise

ABSTRACT Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.

Data Aggregation in Regular Large-Scale IoT Networks: Granularity, Reliability, and Delay Tradeoffs

This article studies data aggregation in large-scale regularly deployed Internet of Things (IoT) networks. The data granularity, in terms of information content and temporal resolution, is parameterized by the sizes of the generated packets and the average interpacket generation time. The generated data packets at the devices are aggregated through static terrestrial gateways. Universal frequency reuse is adopted across all gateways and randomized scheduling is utilized for the IoT devices associated with each gateway. Such network model finds applications in environmental sensing, precision agriculture, and geological seismic sensing to name a few. To this end, we develop a novel spatiotemporal mathematical model to characterize the interplay between data granularity, transmission reliability, and delay. The developed model accounts for several IoT design parameters, which include packet sizes, average generation duty cycle, devices and gateways spatial densities, transmission rate adaptation, power control, and antenna directivity. For tractable analysis, we propose two accurate approximations, based on the Poisson point process (PPP), to characterize the signal-to-interference-plus-noise-ratio (SINR)-based transmission reliability. For the delay analysis, we propose a phase-type arrival/departure (PH/PH/1) queueing model that accounts for packet generation, transmission scheduling, and rate-sensitive SINR-based packet departure. The developed model is utilized to obtain the optimal transmission rate for the IoT devices that minimizes delay. The numerical results delineate the joint feasibility range of packet sizes and interarrival times for data aggregation and reveal significant gains when deploying directional antennas.

Energy Efficiency and Delay Tradeoff in an MEC-Enabled Mobile IoT Network

Mobile-edge computing (MEC) has recently emerged as a promising technology in the 5G era. It is deemed an effective paradigm to support computation intensive and delay-critical applications even at energy-constrained and computation-limited Internet of Things (IoT) devices. To effectively exploit the performance benefits enabled by MEC, it is imperative to jointly allocate radio and computational resources by considering nonstationary computation demands, user mobility, and wireless fading channels. This article aims to study the tradeoff between energy efficiency (EE) and service delay for multiuser multiserver MEC-enabled IoT systems when provisioning offloading services in a user mobility scenario. Particularly, we formulate a stochastic optimization problem with the objective of minimizing the long-term average network EE with the constraints of the task queue stability, peak transmit power, maximum CPU-cycle frequency, and maximum user number. To tackle the problem, we propose an online offloading and resource allocation algorithm by transforming the original problem into several individual subproblems in each time slot based on the Lyapunov optimization theory, which are then solved by convex decomposition and submodular methods. Theoretical analysis proves that the proposed algorithm can achieve a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$[O(1/V), O(V)]$ </tex-math></inline-formula> tradeoff between EE and service delay. Simulation results verify the theoretical analysis and demonstrate our proposed algorithm can offer much better EE-delay performance in task offloading challenges, compared to several baselines.

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Multiplexer (mux) latch is one of the key components for serializer interface to admit communication at Gbps. This work describes the working of a 2:1 mux-latch coupled to a power delivery network (PDN) and a CPU core drawing abrupt current. In comparison to conventional designs, multiplexer and latch operate at the same time, which is quite different because enable inputs are imperative to start latch operation. An analytical model is also derived to understand power delay trade-off and to choose gate sizes to obtain a comparable delay without increasing power. The average power and delay in post-layout are 257.7 μW and 35 ps, respectively, in a 90-nm CMOS, power supply voltage (Vdd) of 1.1 V and a clock switching at 6.25 GHz. However, a 117OC change in temperature at distinct corner allows average power to vary between 32.8 and 64 μW. The corresponding variation is 135–183.7 μW as Vdd switches from 0.75 to 1.1 V. In addition to so, delay changes between 5-14 ps and 3–12 ps for the given change in temperature and Vdd, respectively. Nonetheless, the effective supply voltage VP oscillates with time as the CPU core draws abrupt current. The delay values due to AC noise are found to be different than VP having no noise and the corresponding jitter changes linearly as a function of noise.

Effective Workload Allocation in Fog Device based on Power Consumption and Delay Tradeoff

Fog computing that emerges as an important paradigm, describes decentralized computing architecture between cloud and devices. It includes potential challenges, such as increase in traffic overhead, since all requests are sent to the main server that causes delay, which cannot be tolerated in delay sensitive applications and the usage of inappropriate scheduling causes high power consumption in fog device. These challenges must be overcome by employing effective workload. In this paper, in order to find effective workload allocation based on power and delay tradeoff various scheduling algorithms like SJF (Shortest Job First), FCFS (First Come First Served) and RR (Round Robin) are implemented in fog device and its power and delay trade off are analyzed in fog computing subsystem.

Long-Term Energy Consumption and Transmission Delay Tradeoff in Wireless-Powered Body Area Networks

In this article, we investigate the long-term energy consumption and transmission delay (EC-TD) tradeoff in a wireless-powered body area network that consists of a multiantenna hybrid access point and a number of single-antenna sensor nodes (SNs). The beamforming technique and the simultaneous wireless information and power transfer (SWIPT) technique are adopted. Each SN is equipped with a battery and data buffer for storing harvested energy and sensory data. The long-term energy consumption minimization problem is addressed subject to the constraint of transmission delay. Meanwhile, the residual energy constraints of SNs are considered, which enable the setting up of the available energy of the SNs according to requirements. By employing the Lyapunov optimization theory, the original stochastic optimization problem is transformed into an equivalent instantaneous nonconvex problem in which the long-term EC-TD tradeoff can be adjusted using a system control parameter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> . A joint power and time allocation scheme is then proposed to solve this instantaneous problem. Moreover, based on the derived upper bounds of the long-term energy consumption and data buffer length, we reveal that the proposed resource allocation scheme achieves an EC-TD tradeoff as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$[\mathcal {O}(1/V),\mathcal {O}(V)]$ </tex-math></inline-formula> . Since the value of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> can be adjusted to achieve different energy consumption and transmission delay, the flexibility and applicability of the proposed scheme are enhanced. The simulation results validate the theoretical analysis and verify the effectiveness of the proposed scheme.

Energy–Delay Tradeoff in Adaptive Cooperative Caching for Energy-Harvesting Ultradense Networks

Edge caching in collaborative edge computing (CEC) is a resource-friendly technique to improve energy efficiency and alleviate backhaul link congestion. Caching diverse contents based on the social features among users at energy-harvesting-powered (EH-powered) small base stations can further save on-grid energy, but it may lead to a longer delay to mobile users (MUs). In this article, we focus on an energy–delay tradeoff (EDT) problem in CEC-assisted and EH-powered ultradense networks and propose an EDT-oriented adaptive cooperative caching (EDT-ACC) scheme. We regard delay and energy as two types of cost and introduce a weighted cost function to transform the EDT problem into a cost minimization problem. An alternating optimization based on an improved quantum genetic algorithm (AO-IQGA) is proposed to solve the cost minimization problem. In AO-IQGA, the alternating optimization is utilized to divide the cost minimization problem into two subproblems (adaptive tuning weight subproblem and caching decision subproblem). We improve the quantum genetic algorithm in terms of repairing unfeasible solutions and adaptively updating quantum genes. Numerical results demonstrate the efficiency of the proposed AO-IQGA and illustrate the fundamental tradeoff between delay and energy consumption under different parameters, such as content popularity, storage size, and battery capacity.

Anonymous Stochastic Routing

We propose and analyze a recipient-anonymous stochastic routing model to study a fundamental trade-off between anonymity and routing delay. An agent wants to quickly reach a goal vertex in a network through a sequence of routing actions, whereas an overseeing adversary observes the agent’s entire trajectory and tries to identify the agent’s goal among those vertices traversed. We are interested in understanding the probability that the adversary can correctly identify the agent’s goal (anonymity) as a function of the time it takes the agent to reach it (delay). A key feature of our model is the presence of intrinsic uncertainty in the environment, so that each of the agent’s intended steps is subject to random perturbation and thus may not materialize as planned. Using large-network asymptotics, our main results provide near-optimal characterization of the anonymity–delay trade-off under a number of network topologies. Our main technical contributions are centered on a new class of “noise-harnessing” routing strategies that adaptively combine intrinsic uncertainty from the environment with additional artificial randomization to achieve provably efficient obfuscation.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

PurposeAdvancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).Design/methodology/approachThis paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.FindingsThis paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.Practical implicationsThis paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.Originality/valueThis paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Efficient Energy and Delay Tradeoff for Vessel Communications in SDN Based Maritime Wireless Networks

The maritime communication network is assembled by emergent network technologies. However, the adverse maritime environment impedes the efficiency of resources allocation in maritime communication network. Here we show a joint sleeping scheduling and opportunistic transmission scheme in delay-tolerant maritime wireless communication networks based on software defined networking (SDN) to find a better tradeoff between the energy consumption and the delay. Specifically, an energy-limited delay tolerant networking (DTN) node deployed in the ocean receives/transmits data from/to vessels within its communication range. To further save the energy, a long-term energy minimization problem is formulated with sleeping scheduling and opportunistic transmission. After that, a multi-objective minimization problem of energy and delay is first modeled by Lyapunov optimization (LO), which then is solved by convex optimization. Both mathematical analyses and simulation results demonstrate how the maritime communication network allocates satisfactorily with the proposed allocation scheme.

A systematic design of novel energy efficient 64-bit parallel-prefix adder

ABSTRACT Advancement in CMOS technology demands to revamp the design of basic functional units in digital systems. The binary addition is the basic operation in digital units like microprocessors, digital signal processors and data processing units in ASICs. Scaling down the technology no longer supports power density and energy-efficient digital architectures. The energy-efficient adder design demands the exploration of recurrence structures, existing algorithms, circuit design techniques, system constraints, energy and delay trade-offs. This paper presents the systematic design approach towards the design of an energy-efficient 64-bit parallel-prefix adder. A novel two-bit sum block reduces the power dissipation and the proposed recurrence algorithm further optimises the overall energy consumption. The 64-bit adder is implemented in static CMOS design and simulated in 45, 32, 22 and 16 nm technology nodes to validate the energy efficiency. In 45 nm technology, the proposed 64-bit parallel-prefix adder consumes 64.61% and 15.3% less energy compared to Brent–Kung and Ling adder respectively whereas in 16 nm technology, the proposed adder consumes 57.54% lesser energy than Brent–Kung adder and 14.28% lesser energy compared to the Ling adder.