With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propagation delay is very significant when adjacent wires are transitioning in opposite direction as compared to transitioning in the same direction. As opposite transitions on adjacent wires (called as crosstalk transitions ) have significant impact on propagation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions. We propose selective shielding technique to eliminate crosstalk transitions. We show that the selective shielding technique requires ⌈3 n /2⌉ wires to encode a n -bit bus. SPICE simulations by considering 90nm technology nodes reveal that, for uniformly distributed random data, our technique achieves nearly 39% (21%) delay savings over 10 mm -length uncoded 32-bit bus for pipelined (nonpipelined) data transmission at the cost of nearly 7% energy overhead.
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