Delay Insensitivity Research Articles

Amount and delay insensitivity during intertemporal choice in three neurodegenerative diseases reflects dorsomedial prefrontal atrophy

Patients with Alzheimer's disease and other dementias often make poor financial decisions, but it remains unclear whether this reflects specific failures in decision-making or more general deficits in episodic and working memory. We investigated how patients with Alzheimer's disease, behavioral variant frontotemporal dementia (bvFTD), and semantic variant primary progressive aphasia (svPPA) apply information in an intertemporal choice task between smaller intermediate and larger delayed rewards, with minimal memory demands. Multilevel modeling estimated subject-level sensitivities to three attributes of choice (the relative difference in reward magnitude, delay length, and absolute reward magnitudes) as well as baseline impulsivity. While baseline impulsivity in patients with Alzheimer's disease did not differ from controls, patients with bvFTD and svPPA were more impulsive than controls overall. Patients with Alzheimer's disease or bvFTD were less sensitive than controls to all three choice attributes, whereas patients with svPPA were less sensitive than controls to two attributes. Attenuated sensitivity to information presented during the choice was associated across all subjects with dorsomedial prefrontal atrophy for all three choice attributes. Given the minimal memory demands of our task, these findings suggest specific mechanisms underlying decision-making failures beyond episodic and working memory deficits in dementia.

A GPU Optimized Technique for Scalable Spiking Neural Network Simulation

Simulation studies, in general, heavily rely upon the internal variables of the system / entity in the studies. In case of simulation study of the Spiking Neural Networks (SNNs), the major internal system variables are membrane potentials of the neurons and their respective synaptic inputs which demand to be updated at a sub-millisecond resolution. It would be very apt here to note that this requires thousands of updates to simulate one second of an activity per neuron and this factor makes it imperative to have a highly scalable model to derive some inferences from the simulation. Conventionally, high performance CPUs with high degree of multi-threading were leveraged to conduct simulations and derive inferences. With the advances in the hardware, the degree of parallelism has also increased, especially the GPUs have opened a multitude of avenues to perform SNN simulations at scale. In our pervious works [1, 2, 3], we have demonstrated how GPUs can be leveraged to achieve scalability and performance by using hybrid CPU-GPU approach which have improved the performance as compared to multi-threading on high performance CPUs. In this work, we have focused on hyper parameter tuning of some of the key parameters such as delay insensitivity, time step grouping and the active synapse grouping to achieve greater simulation speed of scalable spiking neural networks

Investigation of copy number variations on chromosome 21 detected by comparative genomic hybridization (CGH) microarray in patients with congenital anomalies

BackgroundThe clinical features of Down syndrome vary among individuals, with those most common being congenital heart disease, intellectual disability, developmental abnormity and dysmorphic features. Complex combination of Down syndrome phenotype could be produced by partially copy number variations (CNVs) on chromosome 21 as well. By comparing individual with partial CNVs of chromosome 21 with other patients of known CNVs and clinical phenotypes, we hope to provide a better understanding of the genotype-phenotype correlation of chromosome 21.MethodsA total of 2768 pediatric patients sample collected at the Genetics Laboratory at Oklahoma University Health Science Center were screened using CGH Microarray for CNVs on chromosome 21.ResultsWe report comprehensive clinical and molecular descriptions of six patients with microduplication and seven patients with microdeletion on the long arm of chromosome 21. Patients with microduplication have varied clinical features including developmental delay, microcephaly, facial dysmorphic features, pulmonary stenosis, autism, preauricular skin tag, eye pterygium, speech delay and pain insensitivity. We found that patients with microdeletion presented with developmental delay, microcephaly, intrauterine fetal demise, epilepsia partialis continua, congenital coronary anomaly and seizures.ConclusionThree patients from our study combine with four patients in public database suggests an association between 21q21.1 microduplication of CXADR gene and patients with developmental delay. One patient with 21q22.13 microdeletion of DYRK1A shows association with microcephaly and scoliosis. Our findings helped pinpoint critical genes in the genotype-phenotype association with a high resolution of 0.1 Mb and expanded the clinical features observed in patients with CNVs on the long arm of chromosome 21.

Narrowband Internet of Things: Evolutions, Technologies, and Open Issues

We are on the threshold of the explosive growth in the global Internet-of-Things (IoT) market. Comparing with the legacy human-centric applications, machine type communication scenarios exhibit totally different characteristics, such as low throughput, delay insensitivity, occasional transmission, and deep coverage. Meanwhile, it also requires the terminal devices to be cheap enough and sustain long battery life. These demands hasten the prosperity of low power wide area (LPWA) technologies. Narrowband IoT (NB-IoT) is the newest Long Term Evolution (LTE) specification ratified by the third generation partner project as one of the LPWA solutions to achieve the objectives of super coverage, low power, low cost, and massive connection. Working in the licensed frequency band, it is designed to reuse and coexist with the existing LTE cellular networks, which endows it with outstanding advantages in decreasing network installation cost and minimizing product time-to-market. In this backdrop, it has been extensively regarded as one of the most promising technologies toward the IoT landscape. However, as a new LTE standard, there are still a lot of challenges that need to overcome. This paper surveys its evolutions, technologies, and issues, spanning from performance analysis, design optimization, combination with other leading technologies, to implementation and application. The goal is to deliver a holistic understanding for the emerging wireless communication system, in helping to spur further research in accelerating the broad use of NB-IoT.

Heavy-Traffic Delay Insensitivity in Connection-Level Models of Data Transfer with Proportionally Fair Bandwidth Sharing

Motivated by the stringent requirements on delay performance in data center networks, we study a connection-level model for bandwidth sharing among data transfer flows, where file sizes have phase-type distributions and proportionally fair bandwidth allocation is used. We analyze the expected number of files in steady-state by setting the steady-state drift of an appropriately chosen Lyapunov function equal to zero. We consider the heavy-traffic regime and obtain asymptotically tight bounds on the expected number of files in the system. Our results show that the expected number of files under proportionally fair bandwidth allocation is insensitive in heavy traffic to file size distributions, thus complementing the diffusion approximation result of Vlasiou et al. [20].

Garden Chrysanthemum Cell Membrane Thermostability and Flowering Heat Delay Differences Among U.S. and South Korean Germplasm

Global warming has created increased nighttime temperatures both in field and greenhouse production of chrysanthemums during flower bud initiation (FBI) and development, causing heat delay or complete cessation of flowering. Integration of breeding and selection for heat delay insensitivity (HDI) has become imperative for greenhouse (cut, potted types) and must be accomplished on a genotypic basis, similar to winterhardiness. This is a breeding objective in the joint garden chrysanthemum breeding project between the Chungnam Provincial Agricultural Research and Extension Services and the University of Minnesota. The objectives of this research were to test 10 genotypes (cultivars, seedlings) from both breeding programs when grown in low-temperature (LT) and high-temperature (HT) short-day (SD) and long-day (LD) conditions (four environments: LTSD, LTLD, HTSD, and HTLD); determine the extent of heat delay and HDI for visible bud date (VBD), flowering, and other phenotypic traits; evaluate relative injury (RI) and cell membrane thermostability (CMT), and to select future parents with lowered RI values, higher CMT, shorter heat-induced flowering delay, and/or HDI. ‘Magic Ball’ and ‘Minnwhite’ had the shortest plant height in HTLD and HTSD, whereas ‘Geumbangul’ had stability for height in all treatments. Lowest long day leaf numbers (LDLN) occurred under LTSD in seven genotypes. However, both ‘Geumbangul’ and ‘Magic Ball’ had complete stability for LDLN across all environments. Sigmoid curves for RI% and temperature were found for all genotypes and environments with R2 = 0.79–0.89. Only ‘Mellow Moon’ had stability or equal VBDs in HTSD, LTSD, and LTLD conditions. This is the first-ever report of stability for VBD across inductive and noninductive HT/LT treatments. Only ‘Centerpiece’ flowered in all environments and also had 0 day of heat for VBD in LT and 1 day of heat delay in HT, as well as three others (Mn. Sel’n. 01-210-43, ‘Autumn Fire’, and ‘Geumbangul’). Few had linear regressions with positive slopes for heat-induced VBD or flowering delay regressed with RI%; most had no slope (R2 ≈ 0.0) for all treatments (‘Centerpiece’, Mn. Sel’n. 01-210-43), whereas others were negative (‘Mammoth™ Dark Bronze Daisy’, Flw LTLD–LTSD). Surprisingly, one linear regression had a slope of R2 = 1.0 (‘Geumbangul’, Flw LTLD–LTSD). These responses are all novel in chrysanthemums. Selecting the best parents in both breeding programs to maximize stability of all traits across these four environments with minimal crossing and selection across generations could be accomplished by stacking parental traits. A crossing scheme involving just three parents is proposed to incorporate stability for all traits in just a few generations.

FDSOI Suitability for Asynchronous Circuits at Sub-VT

Ultra Thin Body and Box Fully Depleted Silicon-on-Insulator (UTBB FDSOI) devices are promising candidates to substitute planar CMOS technology for very large-scale integrated (VLSI) circuits, recently proved to implement complex systems [1]. Their main characteristic is the use of Buried-Oxide (BOX) by providing high channel isolation and excellent electrostatic control over the channel. Due to BOX use is feasible to combine n-/p-type backplane, by allowing different threshold voltages (VT) for the same gate stack, e.g. regular-VT (RVT) and low-VT (LVT) [2]. Their efficient use of a wide body-bias voltage (VBB) range allows a performance management [1, 2], in contrast to other device proposals [3] (i.e. FinFETs). Due to the increasing interest on the Internet of Things, energy efficiency and sub-VT circuits are a hot topic for the research community. Minimum energy point (MEP, i.e. operating voltage where total consumed energy per operation is minimized) monitors their behavior. Sub-VT circuits’ target is medium speed applications (10-100MHz), e.g. wireless sensor networks, medical applications and mobile signal processing [1, 4]. Adders are representative of signal processing architectures, then, their implementation at sub-VT level become of high interest. Below 32nm reliability issues become relevant [4] (e.g. variability). Asynchronous circuits are considered a promising candidate to outperform these threats at sub-VTlevel [4, 5], mainly due to their delay insensitivity. For this, we designed a dual-rail asynchronous 8 bits FA pipelined with four stages, and simulated by using 28nm FDSOI devices. We obtain the MEP regarding the highest consumption operation, from where we obtain both energy consumption and system delay. First, we compare it with its synchronous counterpart. Fig. 1 presents the delay-energy relation for both a-/synchronous 8b FA at MEP, when VBB is shifted. While better VBB influence (i.e. larger delay reduction and lower energy increase) is observed for synchronous proposal, lower energy consumption is always shown for the asynchronous one, proving their higher feasibility at sub-VTlevel. Hereafter, we only study the FDSOI suitability by simulating the asynchronous proposal. Then, we compare different technology options, e.g. FDSOI (LVT and RVT), 28nm Bulk CMOS and 20nm HP PTM FinFET [3]. Fig. 2 presents minor energy consumption for RVT FDSOI-based FA, although shows the largest delay, what highlight their suitability in circuits that are mainly in sleep mode. Nonetheless, Bulk CMOS depicts the worst overall performance, i.e. the highest energy consumption and large delay. Regarding LVT FDSOI and FinFET, we could determine that similar energy values are obtained for both, although FDSOI devices allow us to modify their performance thanks to VBB use. Moreover, note that FinFET models are predictive, in contrast of the “real” ones used for FDSOI. Besides, Fig. 3 depicts the delay-energy relation in function of the VBB, when the asynchronous-based FA uses different number of bits (4, 8 and 16). Larger VBB impact is observed when fewer bits are used, i.e. lower energy consumption and larger delay reduction. Afterwards, Fig. 4 depicts the VBB influence on asynchronous FA performance when environment temperature is modified. We observe wider energy range as temperature increases, contrary to the delay range trend. Moreover, we could manage the VBB to provide a temperature insensitive behavior of our system, i.e. almost constant delay (dashed line), when a proper VBB-shift is applied. Regarding the process variation impact, after 10,000 Monte-Carlo simulations, Fig. 5 depicts that asynchronous FA with larger number of bits shows lower variability impact. Otherwise, when process variations are considered for synchronous-based FA a larger impact is observed, as they break the time constrains in contrast to its asynchronous counterparts. Then, Fig. 6 presents the large number of unexpected behavior attributed to the flip-flop’s time margin violation due to variability, i.e. the signal unfulfilled the setup and hold times. Then, more time margin should be provided to the clock, i.e. system performance lost as frequency reduces, what could be solved by modifying properly VBB[1]. Summarizing, we show the feasibility of asynchronous-based FA as sub-VT circuit (low energy consumption and high variability robustness). Besides, their implementation by FDSOI devices allows a proper management by only modifying VBBin function of the system requirements (performance, temperature and variability).

A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic

We present a new approach for gate-level delay-insensitive asynchronous logic. The new approach uses only conventional synchronous synthesis and computer-aided design tools, as well as conventional standard cell libraries. This new design approach is highly suitable for very low voltage operation compared with traditional static CMOS design. An auto-sleep mode together with supply voltage control logic reduces leakage power consumption. Several benchmark circuits are implemented using IBM 130nm technology to show that the new asynchronous logic approach is robust even when operating in the sub-threshold regime. The layout for each benchmark is generated using Cadence's automatic placement and routing tool. Hspice simulations for both asynchronous and synchronous versions of the benchmark circuits enabled comparison of the delay, area and leakage current. Monte Carlo simulations are performed for each benchmark circuit to demonstrate delay insensitivity for very low supply voltages with substantial threshold voltage ($$V_{T}$$VT) variations.

A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits

Problem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or discrete time. Instead the circuits use handshaking between their components in order to perform the needed synchronization, communication and sequencing of operations. This difference gives asynchronous circuits’ inherent properties in the areas of lower power consumption, higher operating speed and robustness toward variations in supply voltage, temperature and fabrication process parameters, less emission of electromagnetic noise, better modularity, no clock distribution and clock skew problems. Low power consumption seems to be one of the most promising directions and the design reported in this study is one of these examples. Approach: In this study provide different solutions to these problems that the spectrum of existing asynchronous design technique support. It focuses on technique for fine grain two dimensional pipelining that yield ultra high speed at normal power supplies and very low energy at reduced power supplies. The new templates that provide significant performance improvements in quasi delay insensitivity. The key idea is to reduce the complexity of internal circuitry by intelligently reducing concurrency and using an additional wire for communication between pipeline stages. Results: In this study, Quasi Delay Insensitive RSPCHB template has been proposed to enhance the performance is faster with a maximum throughput of 970MHz than the previously designed system. Conclusion: The proposed model has been tested using HSPICE. The authors believe that the proposed design will provide a platform for designing high speed, low power digital circuits such as pipelined multiplier implemented in any application of digital signal processors.

An efficient control point insertion technique for leakage reduction of scaled CMOS circuits

Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the subthreshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in /spl sim/67% leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.

Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware

Formal verification is increasingly important in asynchronous circuit design, since the lack of a global synchronizing clock makes errors due to concurrency (e.g., deadlocks) virtually impossible to detect by means of conventional methods such as simulation. This paper presents a hierarchical approach to asynchronous systems verification using CSP and its model checker FDR. The approach reflects the hierarchical nature of asynchronous hardware synthesis frameworks, for example the Balsa system, and enables the verification of the system at different levels of abstraction against properties such as deadlock, delay insensitivity, conformance and refinement. We demonstrate the feasibility of our approach by automatically detecting errors due to delay sensitivity and deadlock in simple asynchronous hardware components.

Inheritance of Seed Set, Germination, and Day Neutrality/Heat Delay Insensitivity of Garden Chrysanthemums (Dendranthema ×grandiflora) under Glasshouse and Field Conditions

Commercial chrysanthemums are short day (SD) plants. Recently, several day neutral (DN) garden genotypes have been identified. Both glasshouse and garden cultivars vary in heat delay insensitivity (HDI). This research analyzed yield components (seed set, germination, yield potential) and tested a DN/HDI ideotype for its effectiveness. Progeny from a 6 × 6 diallel were embryo rescued, clonal ramats were grown in two environments (glasshouse—long days; field—long to short days) and evaluated for flowering, early flowering response groups, thermozero temperature response, low long day leaf number (LDLN), high leaf initiation rates, and low mean stem lengths of the terminal shoot. Self seed set ranged from 0% to 8% while outcross seed set was 0% to 92%. General and specific combining ability were highly significant for seed set, the reciprocals, and their interactions. Germination averaged 67%, while yield potential was 44%. Cotyledon pigmentation in embryo rescued seedlings was 7% albinos, 15% anthocyanin (transposable elements), and 78% normal (green). SD parents did not flower in either photoperiod although PPSL-10 carried alleles for DN. SD x DN crosses produced some DN progeny and fit a 1:3 chi square ratio (DN:SD), indicating DN to be recessive. However, DN x DN crosses also fit a 3:1 chi square ratio, due to HDI. No progeny flowered within the 3 to 6 week ideotype; visible bud date had a heritability of h2 = 0.50. Most progeny were within the LDLN range (h2 = 0.72). Several leaf initiation rates exceeded the ideotype (h2 = 0.003); plant height also matched the ideotype (h2 = 0.66). Both visible bud and flowering dates require significant improvement before progeny match the DN/HDI ideotype.

Selection of Day-neutral, Heat-delay-insensitive Dendranthem×grandiflora Genotypes

Commercial garden and greenhouse chrysanthemums [Dendranthema ×grandiflora (Ramat.) Kitam. (syn. Chrysanthemum xmorifolium Ramat.)] are facultative short-day plants for flower bud initiation, obligate short-day plants for flower bud development, and are categorized into short-day response groups. Flower initiation can be delayed by high night temperatures. Recent research has identified true day-neutral genotypes. The purpose of this investigation was to test environments for selecting genotypes that are both day-neutral and heat-delay insensitive. One greenhouse and 18 garden genotypes were selected. A series of environments were used to select for day-neutral genotypes and then differentiate between these genotypes for heat delay insensitivity: short days, long days/red light, long days/far red light and high temperatures, and natural day lengths under field conditions. Day-neutral selections from these environments were then grown in a fifth environment of long days/continuous far red and red light with high temperature. Data were collected on the number of days to first and third flower, long day leaf number, stem length, number of strap-shaped leaves subtending the terminal flower, internode lengths, number of nodes with axillary branching, and flower bud development of the first to the sixth flowers. Genotypes required 3 to 8 weeks for complete flower bud initiation/development. Flowering responses in the first four environments were highly significant for both the first and third flowers. Genotypes ranged from obligate short-day to day-neutral for the first six flowers. Three day-neutral genotypes were selected that differed significantly for all traits in the fifth environment; flower bud development with the first six flowers occurred with only one genotype, 83-267-3. Broad sense heritability estimates ranged from h2 = 0.75 for number of nodes with axillary branching, h2 = 0.79 for long day leaf number and number of strap-shaped leaves, to h2 = 0.91 for stem length. An ideotype for day-neutral and heat-delay-insensitive garden chrysanthemums was developed for use in breeding programs.

Delay-insensitive gate-level pipelining

Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit×4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.

468 Inheritance of Day Neutrality and Heat-delay Insensitivity in Dendranthema grandiflora Tzvelv.

Greenhouse and garden chrysanthemums are quantitative short-day (SD) plants for flower bud initiation (FBI) and qualitative (obligate) SD plants for flower bud development (FBD). Continuous or intermittent application of red light in the middle of the dark period (night), inhibits FBI. The chrysanthemum breeding program has been selecting for day-neutral (DN) types, i.e. that will undergo FBI and FBD under any photoperiod. The inheritance of DN was studied using six cultivars (n = 2 SD types, n = 4 DN types) that were crossed in a complete diallel over two crossing periods. Pollinations were replicated and ovules were counted. Histograms of self and cross seed set showed a distribution from 0% to 100%, with the majority of pollinations below 30%. Mean self seed set (2.6%) was less than the mean cross seed set (32.8%), indicating the presence of a self incompatibility system. Parents and F1 progeny were grown under LD conditions (red light, night interruption, 2200-0200 HR) and high temperatures (30 °C day/25 °C night, to screen for heat delay insensitivity). F2 progeny could not be generated due to self incompatibility. The fraction of flowering: non-flowering progeny and the number of days to first flower was recorded on the flowering individuals for comparison with the parents. Due to small progeny numbers, reciprocal crosses were bulked prior to Chi-square tests (1:1, 3:1, 1:3). The number of days to first flower ranged from 27 to 93+ in all progeny with significantly earlier and later outliers present. Most Chi-square tests were not significant, indicating that the inheritance of DN and heat delay insensitivity are not controlled by a single gene. Additive and epistatic effects may also be present.

Automata of asynchronous behaviors

We survey three applications that use finite automata to specify behaviors of concurrent processes in general, and asynchronous circuits in particular. The applications are: verification of concurrent processes, liveness properties, and delay insensitivity of asynchronous networks. In all three cases, we start with a common model of a nondeterministic finite automaton, and then add certain application-specific features. Typically, the added features involve separating the alphabet or the state set of the automaton into several disjoint subsets. For each application we provide the motivation, describe the type of automaton used, define the most important operations, and state some of the key results. For process verification, we describe a BDD-based tool that implements the respective automata and operations.

Analysis and identification of speed-independent circuits on an event model

The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event specification of the circuit behavior in a form of a signal graph. Signal graphs can be viewed either as a formalization of timing diagrams, or as a signal interpreted version of marked graphs (a subclass of Petri nets). The main advantage of this method is that a state explosion is avoided. A restoration of an event specification of a circuit also helps to solve the behavior identification problem, i.e., to compare the obtained specification with the desired specification. We illustrate the method by means of some examples.

A delay insensitive approach to the VLSI design of a DRAM controller

The paper presents an application of Delay Insensitive VLSI design to a real case. A Dynamic RAM Controller, matching the specification of the Intel 8202 ® component, has been designed through a delay insensitive methodology, by using a synthesis system developed by the authors. Delay insensitivity is currently a subject of study due to its promising features for VLSI design. Though formal methods have been widely developed, there is a lack of real applications that prove the capabilities of the delay insensitive approach. The main goal of this paper is to show that a delay insensitive methodology is a suitable automated approach to the design of complex VLSI CMOS circuits.

Simulation Techniques

<p>In the papers surveyed in this thesis a number of simulation techniques are presented together with their applications to several examples. The papers improve upon existing techniques and introduce new techniques.</p><p> </p><p>The improvement of existing techniques is motivated in programming methodology: It is demonstrated that existing techniques often introduce a double proof burden whereas the improved techniques alleviate such a burden. One application is to ensure delay insensitivity in a class of self-timed circuits.</p><p> </p><p>A major part of the thesis is concerned with the deduction and use of two simulation techniques to prove the correctness of translations from subsets of <strong>occam-2</strong> to transputer code.</p>