Delay Fault Testing Research Articles

Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences

Testing for delay faults after chip manufacturing is critical to correct chip operation. Tests for delay faults are applied using scan chains that provide access to internal memory elements. As a result, a circuit may operate under non-functional operation conditions during test application. This may lead to overtesting. The extraction of broadside tests from functional test sequences ensures that the tests create functional operation conditions. When N functional test sequences of length L +1 are available, the number of broadside tests that can be extracted is N · L . Depending on the source of the functional test sequences, the value of N · L may be large. In this case, it is important to select a subset of n ≤ N sequences and consider only the first l ≤ L clock cycles of every sequence for the extraction of n · l ≪ N · L broadside tests. The two-dimensional N × L search space for broadside tests is the subject of this article. Using a static procedure that considers fixed values of N and l , the article demonstrates that, for the same value of N · L , different circuits benefit from different values of N and l . It also describes a dynamic procedure that matches the parameters N and l to the circuit. The discussion is supported by experimental results for transition faults in benchmark circuits.

Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs

Monolithic 3-D (M3-D) integration is an emerging technology that offers significant power, performance, and area benefits for an integrated circuit (IC) design. However, a problem with the 3-D power distribution network in such ICs is that it can lead to high power supply noise (PSN) during the capture cycles in at-speed scan testing for transition delay faults. Therefore, the failure of good chips (i.e., yield loss) resulting from the PSN-induced voltage droop is a major concern for M3-D designs. In this article, we first assess the PSN and voltage droop problems and their impact on path delays for at-speed testing of benchmark M3-D designs. Next, we present an analysis framework to identify test patterns that are most likely to lead to yield loss. We describe a test-pattern reshaping solution based on integer linear programming to make appropriate changes to the test patterns that cause yield loss. Simulation results for four M3-D benchmarks highlight the effectiveness of the proposed solution.

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

Test Architecture for Systolic Array of Edge-Based AI Accelerator

The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used.

Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests

Using both broadside and skewed-load tests for delay faults provides a higher fault coverage and more compacted test sets. An earlier work showed that it is possible to share input test data between broadside and skewed-load tests, and thus reduce the input test data volume. This article develops an algorithm for computing stored tests that can be used for applying both broadside and skewed-load tests in the context of a specific test data compression method. Under this method, a programmable linear-feedback shift register is used for on-chip decompression. In the stored test data, a stored test consists of a seed and two primary input vectors. The seed determines the scan-in state of the applied broadside or skewed-load test as well as the additional scan-in vector required for a skewed-load test. In the algorithm developed in this article, stored tests are computed directly without first computing broadside or skewed-load tests. This avoids situations where the tests cannot be compressed or do not have common input test data.

Built-In Test for Hidden Delay Faults

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years, small delay faults (SDFs) have gained increasing attention as possible indicators of marginal hardware. However, SDFs on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults (HDFs), but so far FAST has mainly been restricted to manufacturing test. This paper presents a fully autonomous built-in self-test approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compaction. In particular, the required test frequencies for HDF detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.

A New Hybrid Test Pattern Generator for Stuck-at –Fault and Path Delay Fault in Scan Based Bist

Testing for delay and stuck-at faults needs a pattern of two checks and test sets square measure sometimes more. Built self-test (BIST) schemes square measure enticing for such comprehensive testing. The BIST check pattern generators (TPGs) for such testing ought to be designed accustomed guarantee high pattern-pair coverage. Within the planned work, necessary and decent conditions to complete/ supreme pattern-pair coverage for consecutive circuit has been derived. A replacement check data-compression theme that's a hybrid approach between external testing and inbuilt self-test (BIST) is analyzed. The planned approach is predicated on weighted pseudorandom testing and uses a unique approach for pressing and storing the load sets. Most existing check generation tools square measure either inefficient in mechanically characteristic the longest checkable methods thanks to the high process complexness or don't support at speed test mistreatment existing sensible design-for-testability structures, like scan style. During this work a check generation methodology for scan-based synchronous consecutive circuits is conferred, below 2 at-speed check methods employed in trade. The approach provides a balanced trade-off between accuracy and potency. Experimental results show promising runtime and fault coverage enhancements over existing ways.

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

On the Generation of SIC Pairs in Optimal Time

The application of single input change (SIC) pairs of test patterns is very efficient for sequential, i.e. stuck-open and delay fault testing. In this paper a novel implementation for the application of SIC pairs is presented and a formal proof of its completeness is provided. The presented generator is optimal in time, in the sense that it generates the n-bit SIC pairs in time $\text n\times 2^{n}$ , i.e. equal to the theoretical minimum. Comparisons with the schemes that have been proposed in the open literature that generate SIC pairs in optimal time, reveal that the proposed scheme requires less hardware overhead.

Path delay test generation at functional level

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

DELAY FAULT MODELS AND METRICS

The delay fault testing has become an important part of the overall test development process. But delay fault testing is not so mature as stuck-at fault testing. The paper surveys various delay fault models, their advantages and limitations. The current trends in test pattern generation for delay faults are analyzed, too. The test pattern gene-ration is directly related to the coverage metrics. The coverage metrics mainly tend to evaluate the quality of path delay fault patterns. The focus is made on two groups of the metrics: non-enumeratve methods and statistical methods. The non-enumerative methods rely on the traditional counting of the paths, which are tested under robust, non-robust, or functional sensitization criteria. The statistical methods relate their computations to the parameters under process variation. The basis of the methods is their weakness. There is still no accepted common metric to evaluate the quality of the delay test patterns. On that base, the paper suggests a new approach to the evaluation of the quality of the delay test patterns. This approach stands on the new term – test confidence level (the ground level, the first level, the second level and etc.). The procedure of the evaluation of test quality for delay faults is presented, too.

IMPACT OF FUNCTIONAL DELAY TEST COMPACTION ON TRANSITION FAULT COVERAGE

Compact test sets are very important for degrading the cost of testing the very large-scale integrated circuits by reducing the test application time. Small test sets also lessen the test storage requirements. The only way to compact functional delay fault tests is to enable multi-input transitions in test pattern pairs. The goal of the paper is to analyze the impact of multi-input transitions in test pattern pairs on the transition fault coverage. The performed research shows that the quality of functional delay fault MIT tests in regard of detection of structural level transition faults is higher than that of functional delay fault SIT tests. However, the application of MIT tests instead of SIT tests for transition fault detection may as well decrease the transition fault coverage. The reasons are in changed conditions of signal propagation from circuit input to circuit output. The possible ways to increase the quality of MIT tests are proposed in this work as well.

Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits

A single path delay fault of a circuit is reduced to a fault in the literal in the equivalent normal form (ENF) that corresponds to the path that acts during the path delay. Based on the analysis of the ENF circuit, we have found properties of pairs of robust and nonrobust test vectors. We show possibilities to reduce the length of the test for path delay faults.

Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs

Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) poses a concern as to whether single-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> testing will suffice for low power nanometric designs. Our analysis shows multi-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3-D stacked ICs (3-D SICs) compared with 2-D ICs because of the larger temperature gradients in 3-D SICs. In this paper, two methods to efficiently enforce the specified temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high-power stimuli to the cores of the IC under test through the test access mechanism. Therefore, no external heating mechanism is required. The tests, high power stimuli, and cooling intervals are scheduled together based on temperature simulations so that the desired temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. The experimental results demonstrate the efficiency of the proposed methods.

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware automatic test pattern generation. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by 22% and 10% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDFs are <; 5%.

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power consumption during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other side, limiting too much the power consumption during test may reduce the defect coverage. Hence, techniques for identifying upper and lower functional power limits are crucial for delay fault testing. Yet, the task of computing the maximum functional peak power achievable by CPU cores is challenging, since the functional patterns with maximum peak power depend on specific instruction execution order and operands. In this paper, we present a methodology combining neural networks and evolutionary computing for quickly estimating peak power consumption. The method is used within an algorithm for automatic functional program generation used to identify test programs with maximal functional peak power consumption, which are suitable for defining peak power limits under test. The proposed approach was applied on the Intel 8051 CPU core synthesized with a 65 nm industrial technology reducing significant time with respect to old methods.

Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage

In nanometric technologies, testing of delay faults in the integrated circuits is becoming mandatory during manufacturing test. Delay fault testing involves two test vectors. Scan based designs is used for delay fault testing with architectural limitations of traditional scan limits the two pattern delay tests that can be applied to a design which results in degraded delay test coverage. Transition delay fault (TDF) coverage improves appreciably by the use of enhanced scan design as it solves the problem by supporting arbitrary delay test vector pairs at the cost of high area overhead. It also needs fast hold signal which is analogous to scan enable signal as in case of LOS testing. Delay testable enhanced scan flip–flop (DTESFF) has been proposed as a low cost DFT technique to achieve high TDF coverage using enhanced scan design without the need of fast hold signal. In this work, a partial DTESFF scheme augments few scan flip–flops with the DTESFF design by choosing scan flip–flops carefully. It attains most of the TDF coverage advantages of a full DTESFF design with reduced area overhead. Significant improvement in TDF coverage for partial enhance scan using DTESFF has been seen on ISCAS’ 89 benchmark circuits.