Test Architecture for Systolic Array of Edge-Based AI Accelerator

Umair Saeed Solangi,Muhammad Ibtesam,Jinuk Kim,Muhammad Adil Ansari,Sungju Park

doi:10.1109/access.2021.3094741

Abstract

The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

Highlights

C URRENTLY, most of the artificial intelligence (AI) applications are running on clouds/datacenters
Recent AI resurgence has been due to deep neural networks (DNNs), which process more hidden layers and result in increased classification accuracy [3]
We propose partial scan based DFT architecture having low overhead (PPA) for edge-based AI hardware

Summary

INTRODUCTION

C URRENTLY, most of the artificial intelligence (AI) applications are running on clouds/datacenters. ASIC based AI hardware accelerators usually favor spatial dataflow architectures, which enable transfer of data between neighboring processing elements (PEs) This pipelined dataflow avoids the need for frequent memory read operations that result in energy optimization [10]. A weight-stationary systolic array allows reusability of weights in implementing subsequent layers of DNN This architecture has been adopted by Google Inc. for their industrial Tensor Processing Unit (TPU) [9] due to its low bandwidth feature. We propose partial scan based DFT architecture having low overhead (PPA) for edge-based AI hardware. A test architecture based on partial scan and systolic pattern loading with a built-in checking circuitry is proposed for weight-stationary systolic array (based on TPU model).

RELATED WORK

SYSTOLIC ARRAY-BASED MATRIX MULTIPLICATION UNIT

PROPOSED TEST ARCHITECTURE

TEST POWER AND TEST TIME FOR AT-SPEED TESTING

VIII. CONCLUSION