Delay-based Physical Unclonable Functions Research Articles

Reliability analysis and comparison of ring-PUF based on probabilistic models

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers.

CalyPSO: An Enhanced Search Optimization based Framework to Model Delay-based PUFs

Delay-based Physically Unclonable Functions (PUFs) are a popular choice for “keyless” cryptography in low-power devices. However, they have been subjected to modeling attacks using Machine Learning (ML) approaches, leading to improved PUF designs that resist ML-based attacks. On the contrary, evolutionary search (ES) based modeling approaches have garnered little attention compared to their ML counterparts due to their limited success. In this work, we revisit the problem of modeling delaybased PUFs using ES algorithms and identify drawbacks in present state-of-the-art genetic algorithms (GA) when applied to PUFs. This leads to the design of a new ES-based algorithm called CalyPSO, inspired by Particle Swarm Optimization (PSO) techniques, which is fundamentally different from classic genetic algorithm design rationale. This allows CalyPSO to avoid the pitfalls of textbook GA and mount successful modeling attacks on a variety of delay-based PUFs, including k-XOR APUF variants. Empirically, we show attacks for the parameter choices of k as high as 20, for which there are no reported ML or ES-based attacks without exploiting additional information like reliability or power/timing side-channels. We further show that CalyPSO can invade PUF designs like interpose-PUFs (i-PUFs) and (previously unattacked) LP-PUFs, which attempt to enhance ML robustness by obfuscating the input challenge. Furthermore, we evolve CalyPSO to CalyPSO++ by observing that the PUF compositions do not alter the input challenge dimensions, allowing the attacker to investigate cross-architecture modeling. This allows us to model a k-XOR APUF using a (k − 1)-XOR APUF as well as perform cross-architectural modeling of BRPUF and i-PUF using k-XOR APUF variants. CalyPSO++ provides the first modeling attack on 4 LP-PUF by reducing it to a 4-XOR APUF. Finally, we demonstrate the potency of CalyPSO and CalyPSO++ by successfully modeling various PUF architectures on noisy simulations as well as real-world hardware implementations.

ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF

Physical Unclonable Functions (PUFs) have been widely considered an attractive security primitive. They use the deviations in the fabrication process to have unique responses from each device. Due to their nature, they serve as a DNA-like identity of the device. But PUFs have also been targeted for attacks. It has been proven that machine learning (ML) can be used to effectively model a PUF design and predict its behavior, leading to leakage of the internal secrets. To combat such attacks, several designs have been proposed to make it harder to model PUFs. One design direction is to use Non-Volatile Memory (NVM) as the building block of the PUF. NVM typically are multi-level cells, i.e, they have several internal states, which makes it harder to model them. However, the current state of the art of NVM-based PUFs is limited to ‘weak PUFs’, i.e., the number of outputs grows only linearly with the number of inputs, which limits the number of possible secret values that can be stored using the PUF. To overcome this limitation, in this work we design the Arbiter Non-Volatile PUF (ANV-PUF) that is exponential in the number of inputs and that is resilient against ML-based modeling. The concept is based on the famous delay-based Arbiter PUF (which is not resilient against modeling attacks) while using NVM as a building block instead of switches. Hence, we replace the switch delays (which are easy to model via ML) with the multi-level property of NVM (which is hard to model via ML). Consequently, our design has the exponential output characteristics of the Arbiter PUF and the resilience against attacks from the NVM-based PUFs. Our results show that the resilience to ML modeling, uniqueness, and uniformity are all in the ideal range of 50%. Thus, in contrast to the state-of-the-art, ANV-PUF is able to be resilient to attacks, while having an exponential number of outputs.

Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA

Physical unclonable functions (PUFs) are gaining traction as an attractive alternative to generating and storing device keying material over traditional secure non-volatile memory (NVM) technologies. In this paper, we propose an engineered delay-based PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and present an analysis of the statistical quality of its bitstrings using data collected from a set of FPGAs subjected to extended industrial temperature-voltage environmental conditions. The SiRF PUF utilizes the Xilinx shift register primitive and an engineered network of logic gates that are designed to distribute signal paths over a wide region of the FPGA fabric using a MUXing scheme similar in principle to the shift-rows permutation function within the Advanced Encryption Standard algorithm. The shift register is utilized in a unique fashion to enable individual paths through a Xilinx 5-input LUT to be selected as a source of entropy by the challenge. The engineered logic gate network utilizes reconvergent-fanout as a means of adding entropy, eliminating bias and increasing uncertainty with respect to which paths are actually being timed and used in post-processing to produce the secret key or authentication bitstring. The SiRF PUF is a strong PUF build on top of a network with 10’s of millions of possible paths.

A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs

As a lightweight hardware security primitive, physical unclonable functions (PUFs) can provide reliable identity authentication for devices of Internet of Things (IoTs) with limited resources. However, the delay-based PUF structures in authentication protocols have static responding behaviors, which make them vulnerable to modeling attacks. To address this issue, many complex PUF designs have been designed to increase the nonlinearity of their models. However, most of them can still be broken by modeling-based machine learning (ML) attacks. In this article, a dynamic responding mechanism for PUF designs to generate dynamic responses is proposed. Different from the concept of logically reconfigurable PUFs, the proposed mechanism does not rely on external inputs to provide reconfiguration signals. And different from the conventional PUF authentication protocols that use large-size linear feedback shift register (LFSR) to extend the master challenge, the proposed scheme uses internally generated dynamic signals to obfuscate the master challenge to generate multiple subchallenges. These subchallenges are then input to the underlying strong PUF to generate multibit dynamic responses. It can prevent an attacker from obtaining valid challenge-response pairs (CRPs) for the underlying PUF. A security authentication protocol is also proposed, the special authentication bit-string design can resist both conventional ML attacks and the latest covariance matrix adaptation evolution strategies (CMA-ES) variant.

PUFs Physical Learning: Accelerating the Enrollment via Delay-Based Model Extraction

The introduction of Physical Unclonable Functions (PUFs) has been originally motivated by their ability to resist physical attacks, particularly in anti-counterfeiting scenarios. In these one-way functions, machine learning, cryptanalysis, and side-channel attacks are common attack vectors threatening the promised PUF's property of unclonability. These attacks often emulate a PUF by employing a large number of Challenge-Response Pairs (CRPs). Some solutions to defeat such attacks are based on a protocol, where a model of the underlying PUF primitives should be extracted during the enrollment phase. In this article, we introduce a novel physical cloning approach applicable to FPGA-based implementations, which allows extracting the PUF's unique physical characteristics with a few number of Challenge-Response Pairs (CRPs), that increases only linearly for a higher number of PUF components. Indeed, our proposed approach significantly accelerates the enrollment phase and makes complex enrollment protocols feasible. Our core idea relies on an on-chip delay sensor, which can be realized by ordinary FPGA components, measuring the unique characteristic of the PUF elements. We demonstrate the feasibility of our introduced technique by practical experiments on different FPGA platforms, cloning a couple of (complex) PUF constructions, i.e., XOR APUF, iPUF, composed of delay-based Arbiter PUFs.

A New Security Boundary of Component Differentially Challenged XOR Pufs Against Machine Learning Modeling Attacks

Physical Unclonable Functions (PUFs) are promising security primitives for resource-constrained network nodes. The XOR Arbiter PUF (XOR PUF or XPUF) is an intensively studied PUF invented to improve the security of the Arbiter PUF, probably the most lightweight delay-based PUF. Recently, highly powerful machine learning attack methods were discovered and were able to easily break large-sized XPUFs, which were highly secure against earlier machine learning attack methods. Component-differentially-challenged XPUFs (CDC-XPUFs) are XPUFs with different component PUFs receiving different challenges. Studies showed they were much more secure against machine learning attacks than the conventional XPUFs, whose component PUFs receive the same challenge. But these studies were all based on earlier machine learning attack methods, and hence it is not clear if CDC-XPUFs can remain secure under the recently discovered powerful attack methods. In this paper, the two current most powerful two machine learning methods for attacking XPUFs are adapted by fine-tuning the parameters of the two methods for CDCXPUFs. Attack experiments using both simulated PUF data and silicon data generated from PUFs implemented on field-programmable gate array (FPGA) were carried out, and the experimental results showed that some previously secure CDC-XPUFs of certain circuit parameter values are no longer secure under the adapted new attack methods, while many more CDC-XPUFs of other circuit parameter values remain secure. Thus, our experimental attack study has re-defined the boundary between the secure region and the insecure region of the PUF circuit parameter space, providing PUF manufacturers and IoT security application developers with valuable information in choosing PUFs with secure parameter values.

Secure lightweight obfuscated delay-based physical unclonable function design on FPGA

The internet of things (IoT) describes the network of physical objects equipped with sensors and other technologies to exchange data with other devices over the Internet. Due to its inherent flexibility, field-programmable gate array (FPGA) has become a viable platform for IoT development. However, various security threats such as FPGA bitstream cloning and intellectual property (IP) piracy have become a major concern for this device. Physical unclonable function (PUF) is a promising hardware fingerprinting technology to solve the above problems. Several PUFs have been proposed, including the implementation of reconfigurable-XOR PUF (R-XOR PUF) and multi-PUF (MPUF) on the FPGA. However, these proposed PUFs have drawbacks, such as high delay imbalances caused by routing constraints. Therefore, in this study, we explore relative placement method to implement the symmetric routing in the obfuscated delay-based PUF on the FPGA board. The delay analysis result proves that our method to implement the symmetric routing was successful. Therefore, our work has achieved good PUF quality with uniqueness of 48.75%, reliability of 99.99%, and uniformity of 52.5%. Moreover, by using the obfuscation method, which is an Arbiter-PUF combined with a random challenge permutation technique, we reduced the vulnerability of Arbiter-PUF against machine learning attacks to 44.50%.

Inconsistency of Simulation and Practice in Delay-based Strong PUFs

The developments in the areas of strong Physical Unclonable Functions (PUFs) predicate an ongoing struggle between designers and attackers. Such a combat motivated the atmosphere of open research, hence enhancing PUF designs in the presence of Machine Learning (ML) attacks. As an example of this controversy, at CHES 2019, a novel delay-based PUF (iPUF) has been introduced and claimed to be resistant against various ML and reliability attacks. At CHES 2020, a new divide-and-conquer modeling attack (splitting iPUF) has been presented showing the vulnerability of even large iPUF variants.Such attacks and analyses are naturally examined purely in the simulation domain, where some metrics like uniformity are assumed to be ideal. This assumption is motivated by a common belief that implementation defects (such as bias) may ease the attacks. In this paper, we highlight the critical role of uniformity in the success of ML attacks, and for the first time present a case where the bias originating from implementation defects hardens certain learning problems in complex PUF architectures. We present the result of our investigations conducted on a cluster of 100 Xilinx Artix 7 FPGAs, showing the incapability of the splitting iPUF attack to model even small iPUF instances when facing a slight non-uniformity. In fact, our findings imply that non-ideal conditions due to implementation defects should also be considered when developing an attack vector on complex PUF architectures like iPUF. On the other hand, we observe a relatively low uniqueness even when following the suggestions made by the iPUF’s original authors with respect to the FPGA implementations, which indeed questions the promised physical unclonability.

Design and Implementation of Multiplexed and Obfuscated Physical Unclonable Function

Model building attack on Physical Unclonable Functions (PUFs) by using machine learning (ML) techniques has been a focus in the PUF research area. PUF is a hardware security primitive which can extract unique hardware characteristics (i.e., device-specific) by exploiting the intrinsic manufacturing process variations during integrated circuit (IC) fabrication. The nature of the manufacturing process variations which is random and complex makes a PUF realistically and physically impossible to clone atom-by-atom. Nevertheless, its function is vulnerable to model-building attacks by using ML techniques. Arbiter-PUF is one of the earliest proposed delay-based PUFs which is vulnerable to ML-attack. In the past, several techniques have been proposed to increase its resiliency, but often has to sacrifice the reproducibility of the Arbiter-PUF response. In this paper, we propose a new derivative of Arbiter-PUF which is called Mixed Arbiter-PUF (MA-PUF). Four Arbiter-PUFs are combined and their outputs are multiplexed to generate the final response. We show that MA-PUF has good properties of uniqueness, reliability, and uniformity. Moreover, the resilient of MA-PUF against ML-attack is 15% better than a conventional Arbiter-PUF. The predictability of MA-PUF close to 65% could be achieved when combining with challenge permutation technique.

Design and Implementation of Multiplexed and Obfuscated Physical Unclonable Function

Model building attack on Physical Unclonable Functions (PUFs) by using machine learning (ML) techniques has been a focus in the PUF research area. PUF is a hardware security primitive which can extract unique hardware characteristics (i.e., device-specific) by exploiting the intrinsic manufacturing process variations during integrated circuit (IC) fabrication. The nature of the manufacturing process variations which is random and complex makes a PUF realistically and physically impossible to clone atom-by-atom. Nevertheless, its function is vulnerable to model-building attacks by using ML techniques. Arbiter-PUF is one of the earliest proposed delay-based PUFs which is vulnerable to ML-attack. In the past, several techniques have been proposed to increase its resiliency, but often has to sacrifice the reproducibility of the Arbiter-PUF response. In this paper, we propose a new derivative of Arbiter-PUF which is called Mixed Arbiter-PUF (MA-PUF). Four Arbiter-PUFs are combined and their outputs are multiplexed to generate the final response. We show that MA-PUF has good properties of uniqueness, reliability, and uniformity. Moreover, the resilient of MA-PUF against ML-attack is 15% better than a conventional Arbiter-PUF. The predictability of MA-PUF close to 65% could be achieved when combining with challenge permutation technique.

The Straight Forward Implementation of the Hardware Security Model for the Internet of Things Devices

Internet of things is the recent progressions in communication technology. It is an affordable computing and implantable technology. Numerous devices like wearable devices, portable devices continuously working for several applications such as smart home, smart city, smart education, smart power, and so on. IoT applications are working under untrusted environments, probably malicious attackers present in the network. Hence, effective security technology is required for IoT applications that can identify and authenticate valid users. IoT applications demand lightweight technology for the security model. Physically Unclonable Functions (PUFs) is a new concept based on the built-in manufacturing variations, it provides hardware security. In this work, we design and implemented 8-bit, 16bit, 32bit and 64 bit delay-based Arbiter PUF, EX_OR Puf, and Feedforward PUFs on two Zynq-7000 XC7Z020 FPGAs (ZedBoard development boards) The proposed delay-based PUF has entirely accomplished on 28 nm Soc-FPGAs. Our focus is on reducing area consumption, increasing speed, and consuming low power.

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Embedding delay‐based physical unclonable functions in networks‐on‐chip

Physical unclonable functions (PUFs) are emerging as security primitives by exploiting the intrinsic device features in various hardware security solutions. This article proposes a mechanism to embed delay-based PUFs, namely arbiter PUF and ring-oscillator PUF, in the network-on-chip (NoC) architecture. These embedded PUFs are constructed by reusing already available hardware resources in NoCs, such as the crossbar switches. Pass transistors, which work as control components, have been added into the delay paths. A 5-port NoC router has been considered and the corresponding 5 × 5 crossbar switches have been analysed after obtaining a suitable layout to embed the delay-based PUFs. The embedded PUFs have been qualitatively analysed for their robustness against variations in supply-voltage. Furthermore, a qualitative study on generating secret keys from the embedded PUFs has been presented. A PUF-specific layout has been considered for implementing the NoC crossbar switches, and for extracting the RC interconnection delays. Monte Carlo simulations have been performed to evaluate the quality metrics of the proposed embedded PUFs for a 64-bit response. Area overheads incurred for realizing the proposed embedded PUFs have been found to be 6.38% and 2.68%, for arbiter PUF and ring-oscillator PUF, respectively. Furthermore, by incorporating the pass transistors in the control components, the reliability metrics have been found to be reasonably improved over traditional constructions of the arbiter and the ring-oscillator PUFs.

Robustness and Unpredictability for Double Arbiter PUFs on Silicon Data: Performance Evaluation and Modeling Accuracy

Classical cryptographic methods that inherently employ secret keys embedded in non-volatile memory have been known to be impractical for limited-resource Internet of Things (IoT) devices. Physical Unclonable Functions (PUFs) have emerged as an applicable solution to provide a keyless means for secure authentication. PUFs utilize inevitable variations of integrated circuits (ICs) components, manifest during the fabrication process, to extract unique responses. Double Arbiter PUFs (DAPUFs) have been recently proposed to overcome security issues in XOR PUF and enhance the tolerance of delay-based PUFs against modeling attacks. This paper provides comprehensive risk analysis and performance evaluation of all proposed DAPUF designs and compares them with their counterparts from XOR PUF. We generated different sets of real challenge–response pairs CRPs from three FPGA hardware boards to evaluate the performance of both DAPUF and XOR PUF designs using special-purpose evaluation metrics. We show that none of the proposed designs of DAPUF is strictly preferred over XOR PUF designs. In addition, our security analysis using neural network reveals the vulnerability of all DAPUF designs against machine learning attacks.

Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs

Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly being used for authentication and key generation in ICs and FPGAs. For space systems, they are a promising approach to meet the needs for secure communications at low cost. To this purpose, it is essential to determine if they are reliable in the space radiation environment. In this work we evaluate the Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring Oscillator PUF. Several major quality metrics have been used to analyze the evolution of the PUF response with the total ionizing dose. Experimental results demonstrate that total ionizing dose has a perceptible effect on the quality of the PUF response, but it could still be used for space applications by making some appropriate corrections.

CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence

Physical Unclonable Functions (PUFs) are devices which exploit manufacturing variability to uniquely distinguish individuals, thus preventing cloning for malicious purposes. With the increasing demand for low-cost devices, PUF designs which can effectively combine small silicon area and power consumption with high resistance to attacks have become of great interest. Unfortunately, many delay-based PUFs have revealed security weaknesses, making them less useful in such domains. This paper presents a novel delay-based strong PUF, the CRPUF (Cylindrical Reconvergence PUF). CRPUF is based on a carefully designed cylindrical XOR fabric, which allows for a large number of delay paths, thus producing a large combination of challenge-response pairs (CRPs) with relatively low transistor count. Simulations based on circuit delay variability models were performed to evaluate CRPUF with respect to well-known delay PUFs. The simulation results were then validated against an FPGA prototype to show that the desirable properties of the CRPUF can be obtained in a realistic physical implementation. Experiments show that CRPUF has Hamming Distance, Hamming Weight and Entropy comparable to the best results published so far, with acceptable levels of Bit Error Rate. Moreover, experiments also show that CRPUF is much more resistant to modeling attacks than other delay and some memory-based PUFs, making it a good candidate to systems which have stringent cost and security constraints.

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function

Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing

With its reprogrammability, low design cost, and increasing capacity, field-programmable gate array (FPGA) has become a popular design platform and a target for intellectual property (IP) infringement. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require permanent secret key storage in the FPGA. In addition, they cannot provide a commercially popular pay-per-device licensing solution. In this paper, we propose a novel IP protection mechanism to restrict IP's execution only on specific FPGA devices in order to efficiently protect IPs from being cloned, copied, or used with unauthorized integration. This mechanism can also enforce the pay-per-device licensing, which enables the system developers to purchase IPs from the core vendors at the low price based on usage instead of paying the expensive unlimited IP license fees. In our proposed binding-based mechanism, FPGA vendors embed into each enrolled FPGA device with a physical unclonable function (PUF) customized for FPGAs; IP vendors embed augmented finite-state machines (FSM) into the original IPs such that the FSM can be activated by the PUF responses from the FPGA device. We propose protocols to lock and unlock FPGA IPs, demonstrate how PUF can be embedded onto FPGA devices, and analyze the security vulnerabilities of our PUF-FSM binding method. We implement a 128-bit delay-based PUF on 28-nm FPGAs with only 258 RAM-lookup tables and 256 flipflops. The PUF responses are unique and reliable against environment changes. We also synthesize a variety of FSM benchmark circuits. On large benchmarks, the average timing overhead is 0.64% and power overhead in 0.01%.

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Silicon physically unclonable functions (PUFs) are circuits that exploit modern manufacturing variations to generate unique signatures for chip authentication and cryptographic key generation. Existing research has focused on improving PUF quality at architectural or design levels, but has ignored opportunities available during fabrication, which is the source of systematic and random variation in (ICs)/PUFs. For typical ICs (where security is not a concern), optical proximity correction (OPC) is used to suppress both these types of variations. However, several prior works have shown that only systematic variations negatively impact PUF quality and random variations are beneficial for PUFs. In this paper, we propose two PUF-aware OPC cost functions: 1) P-OPC generates a PUF lithography mask that increases all variations in PUF circuitry (the opposite of state-of-the-art OPC), and 2) SVC-OPC generates mask patterns that reduce the systematic variation found in PUFs for better quality. Simulation results for ring oscillator (RO) PUFs show that the proposed techniques can improve PUF signature quality compared to current state-of-the-art OPC.