Degradation Of Device Performance Research Articles

Highly Deep Ultraviolet-Transparent h-BN Film Deposited on an Al0.7Ga0.3N Template by Low-Temperature Radio-Frequency Sputtering.

Hexagonal boron nitride (h-BN) is an attractive wide-bandgap material for application to emitters and detectors operating in the deep ultraviolet (DUV) spectral region. The optical transmittance of h-BN in the DUV region is particularly important for these devices. We report on the deposition of thick h-BN films (>200 nm) on Al0.7Ga0.3N templates via radio-frequency sputtering, along with the realization of ultrahigh transmittance in the DUV region. The fraction of the gas mixture (Ar/N2) was varied to investigate its effects on the optical transmittance of BN. DUV light transmittance of as high as 94% was achieved at 265 nm. This value could be further enhanced to exceed 98% by a post-annealing treatment at 800 °C in a N2 ambient for 20 min. The phase of the highly DUV–transparent BN film was determined to be a purely hexagonal structure via Raman spectra measurements. More importantly, these deposition processes were performed at a low temperature (300 °C), which can provide protection from device performance degradation when applied to actual devices.

Effect of OFF-State Stress on Gate-Induced Drain Leakage by Interface Traps in Buried-Gate FETs

The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic random-access memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) and ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized.

Analysis of Negative Bias Temperature Instability Degradation in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors of Different Grain Sizes

This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.

Numerical study of dissolved gas release induced by cavitation in a high speed channel flow

Cavitation often leads to performance degradation of hydraulic devices and, in some cases, to damage of the elements of their constructions (cavitation erosion). Liquids, that are used in technical devices, often contain dissolved gas. Such liquids are of particular interest because cavitation causes release of the dissolved gas into the cavities which can significantly change the flow structure. Mathematical models based on detailed description of all the underlying mechanisms still need development. The approach that was proposed and analyzed in the present study combines a simplified equilibrium model of liquid-vapor phase transition with a non-equilibrium diffusion model describing gas release process. The distributions of the hydrodynamic parameters and the gaseous phase fraction obtained show significant influence of the dissolved gas on evolution of cavitation structures. This is in qualitative agreement with experimental observations regarding the main features of cavitating flows and the behavior of the degassed air. It demonstrates robustness of the proposed simulation algorithm which means that its further development can be a promising way to create a universal model for reliable quantitative prediction of dissolved gas release.

Self‐Healing and Stretchable 3D‐Printed Organic Thermoelectrics

AbstractWith the advent of flexible and wearable electronics and sensors, there is an urgent need to develop energy‐harvesting solutions that are compatible with such wearables. However, many of the proposed energy‐harvesting solutions lack the necessary mechanical properties, which make them susceptible to damage by repetitive and continuous mechanical stresses, leading to serious degradation in device performance. Developing new energy materials that possess high deformability and self‐healability is essential to realize self‐powered devices. Herein, a thermoelectric ternary composite is demonstrated that possesses both self‐healing and stretchable properties produced via 3D‐printing method. The ternary composite films provide stable thermoelectric performance during viscoelastic deformation, up to 35% tensile strain. Importantly, after being completely severed by cutting, the composite films autonomously recover their thermoelectric properties with a rapid response time of around one second. Using this self‐healable and solution‐processable composite, 3D‐printed thermoelectric generators are fabricated, which retain above 85% of their initial power output, even after repetitive cutting and self‐healing. This approach represents a significant step in achieving damage‐free and truly wearable 3D‐printed organic thermoelectrics.

Recent Advances in the Bias Stress Stability of Organic Transistors

AbstractIn this progress report, recent advances in the development of organic transistors with superior bias stress stability and in the understanding of the charge traps that degrade device performance under prolonged bias stress are reviewed, with a particular focus on materials science and engineering methods. The phenomenological aspects of bias stress effects and the experimental methods for investigating charge traps are described. The recent progress in the bias stress stability of organic transistors is discussed in terms of those components that are the main focus of attempts to improve bias stress stability, i.e., organic semiconductor layers, gate dielectrics, and source/drain contacts. A brief summary of this progress is presented and the outlook for future research in this field is assessed. This report aims to summarize recent progress in this field and to provide some guidelines for studying bias stress–induced charge‐trapping phenomena.

Suppression of viewing angle dependence of TEOLED devices with internal nano-wrinkle structure

Abstract In order to suppress the viewing angle dependence of top emission organic emitting diodes (TEOLEDs) with strong microcavity effect, we introduced randomly distributed nano-wrinkle structure beneath highly reflective anode. By applying such nano-wrinkle pattern, viewing angle dependence and color shift could be improved compared with that without nano-structure [e.g. Δ (u’, v’): 0.077 → 0.025]. However, current efficiency reduced more than half. To compensate this problem, we additionally introduced index matching epoxy filler between encapsulation glass and TEOLED device. By this approach, current efficiency drop of device with nano-wrinkle structure could be improved. For example, the efficiency dropped by 7.7% when we filled the epoxy filler between capping layer and glass lid while, it decreased by 30.8% if we don't use epoxy filler. We found that index matching helps to extract more light confined inside TEOLED, so device performance degradation could be minimized. In addition, when we attached a circular polarizer film to these devices, depolarization was observed in most cases, but we were able to achieve a perfect black state from the devices with nano-wrinkle structure underneath reflective anode.

Evaporative electron cooling in asymmetric double barrier semiconductor heterostructures

Rapid progress in high-speed, densely packed electronic/photonic devices has brought unprecedented benefits to our society. However, this technology trend has in reverse led to a tremendous increase in heat dissipation, which degrades device performance and lifetimes. The scientific and technological challenge henceforth lies in efficient cooling of such high-performance devices. Here, we report on evaporative electron cooling in asymmetric Aluminum Gallium Arsenide/Gallium Arsenide (AlGaAs/GaAs) double barrier heterostructures. Electron temperature, Te, in the quantum well (QW) and that in the electrodes are determined from photoluminescence measurements. At 300 K, Te in the QW is gradually decreased down to 250 K as the bias voltage is increased up to the maximum resonant tunneling condition, whereas Te in the electrode remains unchanged. This behavior is explained in term of the evaporative cooling process and is quantitatively described by the quantum transport theory.

Effects of Grain Size on the Electrical Characteristics of Three-Dimensional NAND Flash Memory Devices.

Polysilicon is commonly used as the channel in three-dimensional (3D) NAND flash memory devices. However, degradation of device performance due to grain boundary traps in the channel is a major issue. The saturation on-current level, threshold voltage (Vth), and electron density of 3D NAND flash memory devices with randomly generated grain boundaries were investigated by using three-dimensional technology computer-aided design (TCAD) simulation. The device performance tended to degrade with an increasing number of grains, and the direction of the grains significantly affected the device performance. The large decrease in the electron density of the channel region due to the direction of the grains can be explained according to the formation of the depletion region.

Charge trapping effect in HfO2-based high-k gate dielectric stacks after heavy ion irradiation: The role of oxygen vacancy

The charge trapping effect of HfO2 gate stacks under heavy ion irradiation was evaluated via capacitance-voltage (C-V) measurement and transmission electron microscopy (TEM). Ion irradiation introduced oxygen vacancies into the HfO2 dielectric layer, which located primarily at the interface between HfO2 and Si. The oxygen vacancies act as trapping centers dominating the degradation of device performance after irradiation. The role of the traps on charge trapping in HfO2 gate stacks and the trapped charge stability (i.e. detrapping process) as a function of time were also investigated in this work. The mechanism of how MOS capacitors are affected by irradiation provides a good foundation for future space application of HfO2 gate stacks based integrated circuits.

Observation of Strong Polarization Enhancement in Ferroelectric Tunnel Junctions.

Ferroelectric heterostructures, with capability of storing data at ultrahigh densities, could act as the platform for next-generation memories. The development of new device paradigms has been hampered by the long-standing notion of inevitable ferroelectricity suppression under reduced dimensions. Despite recent experimental observation of stable polarized states in ferroelectric ultrathin films, the out-of-plane polarization components in these films are strongly attenuated compared to thicker films, implying a degradation of device performance in electronic miniaturization processes. Here, in a model system of BiFeO3/La0.7Sr0.3MnO3, we report observation of a dramatic out-of-plane polarization enhancement that occurs with decreasing film thickness. Our electron microscopy analysis coupled with phase-field simulations reveals a polarization-enhancement mechanism that is dominated by the accumulation of oxygen vacancies at interfacial layers. The results shed light on the interplay between polarization and defects in nanoscale ferroelectrics and suggest a route to enhance functionality in oxide devices.

Study of Si Nanowire Surface Cleaning

The Gate-All-Around (GAA) architecture constructed of vertically stacked horizontal Silicon Nano-Wires (Si NWs) are a promising candidate to replace FinFET for device scaling at sub 5-nm technology nodes. In this paper, Si NWs’ release, which is the sacrificial film etching of SiGe 25% (Silicon0.75 Germanium0.25) selective to Si, will be presented. It is known that the boundary layer between Si and SiGe 25% in the multistack is very sharp, since Ge diffusion depth into Si is generally limited up to 1nm. However, the thermal annealing process is known to cause intermixing of SiGe/Si at the boundary layer with an intermixing depth ranging from 1 to 2 nm [1]. In other words, there is a possibility of Ge residue remaining at the Si NWs’ surface after the selective etch of the sacrificial SiGe 25% film using a formulated chemistry [2]. The presence of impurities on the Si NWs channel surface is expected to cause an increase in leakage current causing a degradation in device performance. Therefore, the motivation in this study is to investigate the Ge residue in Si NWs after SiGe:Si selective etching and means of removal them from the Si NWs’ surface. To investigate the surface clean, blanket wafers of 50-nm SiGe 25% on Si were prepared by epitaxial growth. The SiGe 25% layer was then removed using the formulated chemical. These wafers were analyzed by dynamic SIMS and confirmed the diffusion of Ge into Si, which indicates the need of a subsequent surface clean to remaining Ge. At first, various commodity chemicals like HF, HCl and HPM (a mixture of HCl/H2O2/H2O) followed by DIW rinse were evaluated; however, none of these reduced the level of diffused Ge. Similarly, there was no further Ge reduction even with additional process time with the formulated chemical. Finally, APM (a mixture of NH4OH/H2O2/H2O) followed by DIW rinse was investigated, and the Ge concentration on the Si surface was reduced. The H2O2 oxidized Ge to Ge (OH)2, which subsequently dissolved in H2O [3][4]. Furthermore, the H2O2 oxidized the Si surface to SiO2, which was etched by NH4OH. As a result, it is proposed that the intermixing layer of SiGe/Si of Si surface was etched with concomitant reduction of the Ge concentration on the Si surface [5]. The intermixing layer of SiGe/Si has a much lower Ge concentration than SiGe 25%. Therefore, the chemicals that are effective for Si etching should also be effective for removing the intermixing layer of SiGe/Si [6][7]. The result of etching the intermixing layer of SiGe/Si with these chemicals will be presented. In addition, the surface roughness compared to before post process was improved, which is also beneficial for enhancing device performance. Furthermore, the impact of the thermal budget during the annealing process on the removal performance of Ge residue and the difference of intermixing depth of SiGe/Si will be shown. Finally, the most efficient post cleaning for Si NWs will be proposed. In summary, the Ge residue remaining at the Si NWs channel surface, which could not be removed by the formulated chemistry, will be efficiently removed by etching this intermixing layer. It will be shown that an optimized clean after the Si NWs’ release can be effective in removing Ge residue from this Si channel surface. [1] H. Mertens et al., ECS Transactions, 77 (5) 19-30 (2017) [2] K. Komori et al., UCPSS.1662-9787, 282,107-112(2018) [3] K. Komori et al., ECS Transactions, 80(2) 141-146 (2017) [4] N. Cerniglia et al., J. Electrochem. Soc, 109(6) 508-125(1962) [5] G. K. Celler et al., Electrochemical and Solid-State Letters, 3 (1) 47-49 (2000) [6] J. Phys. Chem. C, 118, 4, 2044-2051(2014) [7] O. Tabata et al., Sensors and Actuators A, 34(1) 51-57(1992)

Improvement of Hysteresis in Aluminum Doped Indium-Tin-Zinc-Oxide Thin Film Transistors By Modulating Intrinsic Film Stress of Mo S/D Electrodes

Since first novel report from Hosono’s research group in 2004, numerous studies have been conducted on amorphous oxide TFTs [1]. Because of their various advantages such as high electron mobility, large on-off ratio, and low fabrication temperature, oxide TFTs are expected to play an important role in the next generation display applications. Among several important parameters of oxide TFTs, hysteresis in the transfer curve can give us critical information about types and densities of defects in the TFTs. In the case of clockwise hysteresis, it is generally known that the hysteresis occurs when there are electron traps in the bulk region of the active layer, or interface between the active front channel and the gate insulator. Therefore, until now, studies have mainly focused on reducing the hysteresis by optimizing several engineering conditions such as deposition method, deposition temperature, post-annealing temperature. On the other hand, as far as we know, the intrinsic film stress, which is determined by the process conditions during the thin film deposition, has not been discussed much in terms of performance of oxide TFT. Especially in the large screen display applications, the intrinsic film stress of metal contacted with active layer, needs to be carefully handled because carrier trap sites may be generated due to high film stress , resulting in degradation of device performance. Nevertheless, there have been few studies about the change of device properties caused by the intrinsic film stress in the oxide TFT. Thus, in this study, we investigated the relationship between the intrinsic film stress of metal and the hysteresis phenomenon in the aluminum doped indium-tin-zinc-oxide (Al-ITZO) TFT. First, we fabricated molybdenum (Mo) thin films with different intrinsic film stress by intentionally controlling the argon working pressure during the sputtering process [2]. The intrinsic film stress values of Mo thin films were calculated by Stoney equation which uses the change of substrate curvature before and after the thin film deposition. According to the calculated results, high-stress Mo and low-stress Mo showed intrinsic tensile stress values of 1920.7 MPa and 143.9 MPa, respectively. Then, we fabricated back-channel-etched structured Al-ITZO TFTs by applying those molybdenum Mo thin films as source and drain (S/D) electrodes, and compared hysteresis of each TFT. It was confirmed that the modulation of the intrinsic film stress of S/D electrodes affected the clockwise hysteresis characteristics of the TFTs. As shown in Figure 1, in the case of TFT using high-stress S/D, hysteresis was about 1.4V larger than the TFT with low-stress S/D in both of short and long channel TFT. This result is interesting because the S/D electrodes with the same material but different film stress on the back surface of the active layer induced a change of the hysteresis. Therefore, we assumed that the stronger tensile stress of high-stress S/D induced larger hysteresis in the TFT, and X-ray photoelectron spectroscopy (XPS) depth profile method was used for further analysis. By analyzing the XPS results, it was possible to compare the difference of the chemical state at the front channel after depositing S/D electrodes with different film stress values, and consequently, hysteresis difference could be explained. Through this research, we expect new engineering perspective can be provided in display industries. [1] Nomura, Kenji, et al. "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors." Nature 432.7016 (2004): 488. [2] Windischmann, Henry. "Intrinsic stress in sputter-deposited thin films." Critical Reviews in Solid State and Material Sciences 17.6 (1992): 547-596. This work has supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT)(2018R1A2A3075518). Figure 1

Atomic Layer Deposition of Al2O3 with Alcohol Oxidants for Impeding Substrate Oxidation

Atomic layer deposition (ALD) is a vapor phase thin film deposition technique based on self-limited surface reaction. ALD processes consist of two (or more than) half-reactions. The first half-reaction is the self-limiting adsorption of precursor molecules which contain core metal atoms; the second half reaction is the self-limiting reaction between surface adsorbed precursor molecules and reactants. Since ALD could deposit thin films with high quality, good uniformity, high conformality, and sub-nanometer thickness controllability, [1-3] ALD has been regarded as one of the most suitable deposition technologies for semiconductor device fabrication. Since thin films of alumina (Al2O3) have wide range of applications such as high-k dielectric material for electronic devices, mechanical and chemical protective coatings, diffusion barriers, and optical coatings, [4-7] ALD of Al2O3 process is the mostly and thoroughly studied. For the deposition of Al2O3, trimethylaluminum (TMA) have been the most widely used for Al precursor due to its high vapor pressure and reactivity. And water (H2O) is widely utilized as the oxygen source in ALD Al2O3 processes, because since H2O often shows facile ligand exchange reaction during ALD. However, ALD Al2O3 processes with H2O reactant showed undesirable substrate oxidation issue. For example, there was an unwanted interface oxide between ALD deposited Al2O3 film and Si substrate. The interface oxide could reduce the dielectric constant of the deposited thin films and increase leakage current density. [8-9] Especially, the oxidation of substrate is critical issue for 2 dimensional (2D) transition-metal dichalcogenides (TMDCs) based field effect transistors (FETs). From our previous results, the oxidation of MoS2 by H2O considerably degraded device performance. [10-11] To avoid the oxidation of substrates and improve device performance, it is necessary to develop a new ALD process by using oxidants with lower oxidation potential than that of H2O. Despite its technical importance, ALD Al2O3 processes with weaker oxidants such as alcohols have rarely been investigated. [8] For this reason, the chemical reaction mechanism between surface adsorbed precursor and reactant has not been clearly identified. In this work, we fundamentally investigated ALD process Al2O3 on Si substrate, using TMA and various alcohol oxidants (methanol (MeOH), ethanol (EtOH), and n-propanol (n-PrOH)). Furthermore, we investigate the reaction mechanism of various alcohol oxidants during ALD of Al2O3 with TMA. Density functional theory (DFT) calculations at B97D3 level of theory were performed using Gaussian 09 suite of programs. Our developed ALD processes showed typical ALD growth characteristics. The saturated growth rates with MeOH, EtOH and n-PrOH were 0.10, 0.96, and 0.74 Å/cycle, respectively. From the calculation results, we revealed that the beta-hydrogen transfer reaction of EtOH and n-PrOH could easily oxidize surface methyl group into surface hydroxyl. The results could be applicable to highly integrated semiconductor devices fabrication and 2D TMDC based FET fabrication processes.

Parasitic Cell-to-Cell Heat Transfer in Reram Arrays and Thermally Induced Memory Cell Performance Degradation

Resistive RAM memory are manufactured in a cross-point architecture. A cross-point, where a memory cell is located, is an intersection of vertical and lateral metal lines for the active and inert electrodes of a resistive memory cell. The two metal electrodes are separated by a dielectric such as TaOx. We have manufactured resistive ReRAM cells Cu/TaOx/Pt/Ti and Cu/TaOx/Rh/Cr. The thickness of TaOx is 25 nm. The thickness of the Cu, Pt, Ti, Rh, and Cr layers is 150 nm, 50 nm, 20 nm, 50 nm, 20 nm, respectively. All layers have been deposited using e-beam PVD. The line width of the Cu, Pt/Ti and Rh/Cr varies from 5 μm to 35 μm. The distance between the lines is ca 150 μm. The latter parameter is a characteristic distance for heat transfer between the cells. Fresh isolated Pt/Ti and Rh/Cr devices display similar switching properties, with very similar Vform, Vset, Vreset, and Ron distributions. The inert electrode of Rh/Cr, has roughly twice larger heat conductivity than Pt/Ti. The heat conductivities for Pt, Ti, Rh, and Cr are 72, 22, 150, and 94 W/(mK), respectively, much inferior to the heat conductivity of Cu at 385 W/(mK). When one cell in the array is repeatedly switched on and off, a certain amount of heat is being deposited in the device. The switching heat is dissipated to the environment mainly by the electrode metal lines. Our results show that the heat deposited in a device lingers for some time in the vicinity of the device and spreads to neighboring devices via the common electrode lines. Experiments show that just after repeated set-reset cycles of one device, the performance of neighboring devices is degraded when they have a metal line in common with the heated device. The question became how, in absence of a temperature probe, to measure such heat transfer and the resulting device degradation quantitatively. To probe into such degradation we have chosen specific set conditions of the device at a compliance current (Icc) of 10 uA. For lower Icc, the on-state is volatile, and for larger Icc the cell is non-volatile and the filament is stable, Thus, Icc=10 uA is a stability border case. A fresh device under such condition can be switched in sequence maximally 13-15 times. We find that for devices affected immediately after heating of a neighboring device this maximal number of switching cycles decreases significantly. We have measured the maximum number of switching cycles for neighboring devices along the Cu and along the Pt electrode lines. Because of the higher heat conductivity, the performance degradation for a Cu line extends to more distant neighboring cells than in the case of Pt/Ti electrode lines. After some cooling off period the devices displaying performance degradation recover quickly to the pre-stress performance level. We find that the cooling off period is shorter for the Cu lines than for the Pt/Ti lines. We observe also that the performance impact on the neighboring cells is larger for lines with small cross section (thickness × width) than for those with large cross section. However, for a short time (couple of minutes), the fast heat dissipation extends over a larger distance within which the devices may be affected by the heated device. This poses a dilemma in terms of the sequence, allowable frequency and location of the cells to be programmed. Interestingly, cells which do not share neither of the two metal lines with the heated device (even if geometrically close to it), are mostly unaffected by the heating of the stressed cell, provided there is no direct heat conductor path connecting the device with heat source. This condition is fulfilled when the intermediate cells lying in the path between the monitored device and the heated device are in the off-state. However, if the intermediate cells are in the on-state, they provide a direct electrical (thus a direct heat) path from the heated device to the tested device, leading to the performance degradation of the probed cell. The heat conduction is also affected by the cross-sections of the metal lines. In commercial application the width and thickness of such metal lines are on the order of couple 10's of nm rendering the commercial arrays 100 times tighter in lateral dimensions than our samples. In nanowires the heat transport is no longer diffusive but ballistic which is known to make for a less efficient heat transport. Hence, for commercial memory arrays the nonlocal heating effects and the resulting device performance degradation are likely be more pronounced.

High Thermal Boundary Conductance across Bonded Heterogeneous GaN-SiC Interfaces.

High-power GaN-based electronics are limited by high channel temperatures induced by self-heating, which degrades device performance and reliability. Increasing the thermal boundary conductance (TBC) between GaN and SiC will aid in the heat dissipation of GaN-on-SiC devices by taking advantage of the high thermal conductivity of SiC substrates. For the typical growth method, there are issues concerning the transition layer at the interface and low-quality GaN adjacent to the interface, which impedes heat flow. In this work, a room-temperature bonding method is used to bond high-quality GaN to SiC directly, which allows for the direct integration of high-quality GaN with SiC to create a high TBC interface. Time-domain thermoreflectance is used to measure the GaN thermal conductivity and GaN-SiC TBC. The measured GaN thermal conductivity is larger than that of grown GaN-on-SiC by molecular beam epitaxy. High TBC is observed for the bonded GaN-SiC interfaces, especially for the annealed interface (∼230 MW m-2 K-1, close to the highest value ever reported). Thus, this work provides the benefit of both a high TBC and higher GaN thermal conductivity, which will impact the GaN-device integration with substrates in which thermal dissipation always plays an important role. Additionally, simultaneous thermal and structural characterizations of heterogeneous bonded interfaces are performed to understand the structure-thermal property relation across this new type of interface.

Numerical study of submerged impinging jets for power electronics cooling

Advancements in power electronic technologies require devices which are small, reliable and capable of handling large power levels. Despite efficiencies of electronic components are usually above 90%, wasted thermal powers can result in heat flux densities in the order of hundreds of W/cm2.To avoid degradation in performance and lifetime of these electronic devices, specific active cooling systems need to be adopted and submerged impinging jets represent one of the most promising solutions. In the present paper a numerical study of different cooling jet configurations is presented, and high-efficiency solutions are sought. The configurations investigated are obtained by varying nozzle diameter, aspect ratio, arrangement and number of jets. Simulations are performed on a simplified computational domain which involves a single rectangular chip (representing the heat source) separated from the coolant by a multi-material solid stack.As compared to more classical solutions like pin fins, submerged impinging jets represent an efficient technique for the cooling of power electronics. Heat is exchanged at low pumping power level. Array of jets are flexible in terms of geometry and can be specifically designed to control temperatures in critical spots.

Study of Si Nanowire Surface Cleaning

The Gate-All-Around (GAA) Field-Effect-Transistor (FET) is proposed as a promising candidate to replace Fin FET. In GAA architecture, Si Nanowires (NWs), which are fabricated by selective etching of SiGe from Si/SiGe multilayer fin structure, are used as channel. One of the concerns for fabricating GAA architecture is residual Ge, which is diffused SiGe from the Si/SiGe multilayer stack, in the Si NWs after their release. This Ge residue is a concern, since it could cause a degradation in device performance. The roughness of the Si NWs’ surface, which is a further factor in the degradation of device performance, was also examined. In this study, residual Ge removal and surface roughness with commodity chemistry was investigated. Finally, it was confirmed that residual Ge could be completely removed from Si without increasing Si surface roughness by dH2O2.

Nanoconfining Optoelectronic Materials for Enhanced Performance and Stability

The solution processing of optoelectronic active layers promises to usher in a new era of technologies, from rollable displays to smart textiles, but critical challenges remain in the processing of these materials. While solution-based deposition of these compounds, including organic small-molecules and polymers and metal–halide perovskites, is key to driving down manufacturing costs, the rapid, uncontrolled nature of solution processing invariably results in the formation of kinetically trapped films, with heterogeneities and defects spanning multiple length scales that degrade device performance. Given such finite time, usually on the order of seconds, for molecules to organize as solvent evaporates from the active layers, the use of nanoporous scaffolds to select for desired crystallization outcomes is a promising approach to addressing this critical issue. As the size of crystals decreases, their surface free energy plays an increasingly important role in dictating their morphology and structure. By c...

Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation

As a 3D integration technology, the through silicon via (TSV) has attracted increasing interest owing to the need for reducing energy consumption in devices. However, high thermal stress is induced owing to large mismatches in the coefficients of thermal expansion (CTE) between the copper via and the silicon (Si) substrate in TSVs, causing critical reliability issues such as the performance degradation of stress-sensitive devices. We proposed a novel structure, the annular-trench-isolated (ATI) TSV, as a possible solution for the reliability issues caused by thermal stress in 3D packaging technology with TSVs. The ATI TSV structure has an extra Si ring outside of the metal core. We successfully fabricated an ATI TSV with a 10-μm diameter using separate etching processes for the insulator trench and the metal core. A narrow insulator trench with a thickness of 2 μm was formed, and its aspect ratio (AR) was as high as 10. A Si ring with a thickness of 1 μm remained between the insulator layer and the metal core. In order to study the stress level of the ATI TSV, we investigated the radial and axial thermal stresses using polarized Raman spectroscopy and a simulation by the Finite Element Method. Agreement between the simulation results and the measured stress data was observed and validated the simulation model. Furthermore, we revealed that the Si substrate of the ATI TSV had a lower thermal stress level than the regular TSV. This was accomplished using the validated simulation model owing to the redistribution of stress by the Si ring in the ATI TSV.