Defects In ICs Research Articles

A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs

Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.

Test Structure Design for Defect Detection during Active Thermal Cycling.

Integrated power ICs acting as smart power switches for automotive or industrial applications are often subjected to active thermal cycling. Consequently, they undergo significant self-heating and are prone to various failure mechanisms related to the electro-thermo-mechanical phenomena that take place in the device metallization. In this article a test structure consisting of a lateral DMOS transistor equipped with several integrated sensors is proposed for metallization fatigue assessment. The design of the test structure is presented in detail, alongside with design considerations drawn from the literature and from simulation results. The testing procedure is then described, and experimental results are discussed. The experimental data provided by the integrated sensors correlated with the electro-thermal simulation results indicate the emergence of a failure mechanism and this is later confirmed by failure analysis. Conclusions are further drawn regarding the feasibility of using the proposed integrated sensors for monitoring defects in power ICs.

Techniques for SAT-Based Boolean Reasoning on Multiple Faults Affecting Logic Cells and Interconnects in Digital ICs

We propose a new method for SAT-based Boolean reasoning on multiple defects in digital ICs. Although it does not explicitly consider a specific fault model such as model-based techniques, it allows us to consider more realistic cases than model-free approaches. In particular, it can be used to account for (a) faults resulting in monotonic errors at the output of a cell and (b) faults, such as breaks or bridgings, that may corrupt the propagation of a signal from its fan-out branches. The model can be used for either standard gates or more complex combinational modules. Examples are shown for applications requiring the consideration of multiple defects such as fault diagnosis and reliability analysis. The feasibility of the proposed approach is assessed by results on a set of combinational benchmarks.

Topological and real charge of Bjerrum defects in ices Ih and Ic

Two mechanisms for the interaction of Bjerrum defects in ices are considered. (i) In the lattice ice models, the defects are topological charges interacting by the entropy of proton disorder. The charge magnitude is calculated by fitting the potential of mean force of a pair of defects (minus log of the simulated 3D distribution function) in the periodic boundary conditions to the Ewald summation energy. (ii) At the atomic level, the effective Coulomb charges for several classical water models are calculated as a sum of Gaussian-smoothed partial charges. The topological charge is equivalent to % of the Bjerrum defect real charge.

Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing

Three-dimensional Integrated Circuits (3D ICs) based on Through-Silicon Vias (TSVs) provide many benefits, such as high density, high bandwidth and low-power consumption. However, defects in TSV due to complex fabrication steps decrease the yield and reliability of 3D ICs. Therefore each die should be tested before it is stacked through pre-bond test. Pre-bond test and defect identification of TSVs are extremely important to screen out defective TSVs early in the manufacturing flow. Also, test cost minimization is one of the key issues of the testing process. The existing test time minimization solutions for pre-bond test consider random TSV defects. However, in practice clustered TSV faults are quite common. In this paper, we propose a novel test time minimization technique to address both random and clustered defect distributions. The proposed solutions are based on recursive bi-partitioning and padding of test sessions to minimize the number of required test sessions as well as test time. Simulation results show that the proposed method can achieve more than 50% reduction in test time for a 20-TSV network with four faulty TSVs compared to serial testing approach. The proposed algorithm also pinpoints the defective TSVs in a TSV network with a reduced test time compared to prior works.

TIVA Measurements with Visible and 1064-nm Lasers

Abstract Laser stimulation is widely used to reveal defects in ICs through either heating or photonic effects. The standard approach is to use lasers with wavelengths above the bandgap wavelength of silicon to create localized heating and below it to generate photocurrent. In practice, most FAs use 1340 nm (IR) lasers for TIVA measurements and either 532 nm (visible) or 1064 nm (near IR) lasers for LIVA analysis. However, as this article demonstrates, visible and near IR lasers can also be used for TIVA analysis and, in some cases, may be preferrable based on signal strength and spatial resolution.

Parent stress across molecular subtypes of children with Angelman syndrome.

Parenting stress has been consistently reported among parents of children with developmental disabilities. However, to date, no studies have investigated the impact of a molecular subtype of Angelman syndrome (AS) on parent stress, despite distinct phenotypic differences among subtypes. Data for 124 families of children with three subtypes of AS: class I and II deletions (n = 99), imprinting centre defects (IC defects; n = 11) and paternal uniparental disomy (UPD; n = 14) were drawn from the AS Rare Diseases Clinical Research Network (RDCRN) database and collected from five research sites across the Unites States. The AS study at the RDCRN gathered health information to understand how the syndrome develops and how to treat it. Parents completed questionnaires on their perceived psychological stress, the severity of children's aberrant behaviour and children's sleep patterns. Children's adaptive functioning and developmental levels were clinically evaluated. Child-related stress reached clinical levels for 40% of parents of children with deletions, 100% for IC defects and 64.3% for UPD. Sleep difficulties were similar and elevated across subtypes. There were no differences between molecular subtypes for overall child and parent-related stress. However, results showed greater isolation and lack of perceived parenting skills for parents of children with UPD compared with deletions. Better overall cognition for children with deletions was significantly related to more child-related stress while their poorer adaptive functioning was associated with more child-related stress. For all three groups, the severity of children's inappropriate behaviour was positively related to different aspects of stress. How parents react to stress depends, in part, on children's AS molecular subtype. Despite falling under the larger umbrella term of AS, it is important to acknowledge the unique aspects associated with children's molecular subtype. Identifying these factors can lead to tailored interventions that fit the particular needs of families of children with different AS subtypes.

Drosophila piwi Mutants Exhibit Germline Stem Cell Tumors that Are Sustained by Elevated Dpp Signaling

Drosophila Piwi is the founding member of a gonadal clade of Argonaute proteins that serve as silencing effectors for ∼26-32 nt Piwi-interacting RNAs (piRNAs) [1], and piwi mutants exhibit dramatically rudimentary ovaries [2]. It was proposed that somatic Piwi maintains germline stem cells (GSCs) by promoting Dpp signaling, presumably via cap cells that form the somatic niche for GSCs [3-5]. However, we unexpectedly observed that piwi mutants exhibit high-frequency GSC-like tumors that persist throughout adult life. Multiple readouts demonstrated hyperactive Dpp signaling in piwi mutants, including the failure to express the germline differentiation factor bag-of-marbles (bam), and restoration of bam expression relieved piwi GSC-like tumors. Tissue-specific rescue and knockdown experiments indicate that Piwi is not required in cap cells, the source of niche Dpp, but instead is required in gonadal intermingled cells (ICs, the progenitor cells of escort cells). Adult-specific knockdown of dpp in escort cells substantially rescued piwi tumors, demonstrating that they are driven by excess Dpp signaling. However, the temporal requirement for piwi to restrict GSC numbers was much earlier, during the wandering third-instar larval stage. Indeed, piwi mutant larval gonads exhibited defective morphology and loss of Bam. Our data indicate that loss of Piwi causes defects in ICs and escort cells, leading to ectopic Dpp signaling and consequent blockage of GSC differentiation.

New insights into pharyngo‐esophageal bolus transport revealed by pressure‐impedance measurement

Pharyngeal propulsion, strength of peristalsis and esophago-gastric junction (EJG) resistance are determinants of esophageal bolus transport. This study used pressure-impedance methods to correlate pharyngo-esophageal function with the esophageal bolus trajectory pathway and pressures generated during bolus transport. Pharyngo-esophageal pressure-impedance measurements were performed in 20 healthy adult controls. Pharyngeal automated impedance manometry (AIM) analysis was performed to derive pharyngeal swallow function variables. The esophageal time of nadir impedance (TZn) was used to track bolus trajectory pathway. The inflection, or flow stasis point (FSP), of the trajectory curve was determined as were the pressures within the bolus (PZn) above and below the FSP. The size of 20 mmHg isocontour defect (20 mmHg IC defect) measured the integrity of the peristaltic wave. For viscous boluses, weaker pharyngeal bolus propulsion correlated with the FSP being located higher in the esophagus. Pressure within the bolus was observed to increase at the FSP and below the FSP in a manner that correlated with the magnitude of esophageal peak pressures. Larger 20 mmHg IC defects were associated with lower pressures within the bolus at the FSP and below. The FSP of the bolus trajectory pathway appears to represent a switch from bolus propulsion due to pharyngeal mechanisms to bolus propulsion due to esophageal mechanisms. 20 mmHg IC defects significantly reduce bolus driving pressure at or below the FSP.

Electrical Test Method for Interconnect Open Defects in 3D ICs

In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz.

Characteristic Recognition of IC Chip’s Micro-Topography Defects Based on Image Projection Transformation and Energy Optimization Modeling

For accurate inspecting the micro-topography defects of IC chip, characteristic recognizing method of topography defects based on image projection transformation and energy optimization modeling is presented. First the topography conjugate images have been obtained by high-definition CCD cameras from different space positions, and then we extracting the relative positions of several selected IC defect characteristic-points, through establishing the relationship of image projecting transformation these point’s absolute three-dimensional coordinates can be calculated and determined, with energy optimization modeling the controlling curves are fitted, and then the defect topography in each enclosing spatial region which constituted by these controlling curves is structured. Mathematical characteristics are established according to the topography model, after training and adjusting BP network repeatedly the topography defects can be characteristic-recognized, and the recognizing results are gotten. In this experiment the performance comparison and analysis are implemented in several typical recognizing methods of image characteristic, which prove this new method’s accuracy and reliability and provide new idea for following IC chip’s precise detection.

Understanding the Effects of Local Structures on TIVA Profiles Using Thermal Modeling and Simulation

Abstract Thermally-induced voltage alteration (TIVA) is a laser-based method for localizing interconnect defects in ICs. Its main limitation is that the laser must heat the defect and change its resistance sufficiently to produce a measurable voltage alteration. Anything that interferes with laser absorption or alters defect heating makes TIVA less effective. This article presents the results of a study on the effects of local structures on TIVA imaging. The authors selected a polysilicon-metal test structure as the focal point of their study, which entailed experimental investigation along with modeling and simulation. It was found that the TIVA profiles on this structure are strongly influenced by local geometry, particularly the variation of interlevel silicon dioxide thickness and the placement of polysilicon lines with respect to aluminum lines. Understanding such relationships is essential for locating defects using TIVA techniques.

Testing Structure for Detection of Poly Stringer Defects in CMOS ICs

A testing structure was developed to more effectively detect the poly stringer defects in contemporary CMOS ICs. This structure is much more sensitive to poly stringer defects and is closer to the real product layout than the currently widely used structure using an active dummy underneath a poly comb. Many testing structure pieces manufactured in a 0.11 μm copper process line were used to compare the current design with the conventional testing structure. The data shows that the new structure more efficiently detects poly stringers. The results also show that the poly stringers are related to the shallow trench isolation (STI) width. This structure can be used to identify new designs for manufacturing rules for the active space. Thus, this method is very useful for IC foundries to detect poly stringers and to characterize the processing line capability and tune the process recipe to improve product yields.

Diagnosis of Multiple-Voltage Design With Bridge Defect

Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.

Advanced Defect Characterization by STEM Analysis

Abstract Localizing defects in one-of-a-kind failures can take days, weeks, or even months, after which a detailed physical analysis is conducted to determine the root cause. TEM and STEM play complimentary roles in this process; TEM because of its superior spatial resolution and STEM because it produces images that are easier to interpret and is less susceptible to chromatic aberrations that can occur in thicker samples. In the past, the use of STEM in FA has been limited due to the time required to switch between imaging modes, but with the emergence of TEM/STEM microscopes with computer controlled lenses, the use of STEM is increasing. This article provides an overview of STEM techniques and present examples showing how it is used to characterize subtle and complex defects in ICs.

Advanced Defect Isolation Utilizing Image Intensity Analysis

Abstract Image enhancement has proven helpful for locating defects in ICs. This article discusses two image analysis techniques, image comparison and intensity profiling, and shows how they reveal defects that would otherwise be missed.

Effect of BIST Pretest on IC Defect Level

In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to ensure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to get rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when it may be worthwhile to perform it.

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

A resistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor between two circuit nodes that should be connected. A stuck-open (SOP) defect is a complete break (no current flow) between two circuit nodes that should be connected. Conventional single stuck-at fault diagnosis cannot precisely diagnose these two defects because the test results of defective chips depend on the sequence of test patterns. This paper presents precise diagnosis techniques for these two defects. The diagnosis techniques take the test-pattern sequence into account, and therefore, produce precise diagnosis results. Also, our diagnosis technique handles multiple faults of different fault models. The diagnosis techniques are validated by experimental results. Twelve SOP and one resistive-open chips are diagnosed out of a total of 459 defective chips.

Methods of reducing defects in GaAs ICs

This is a recount of a quality improvement journey. An admirable goal is to reach zero defects. At a resolution of parts per million, “zero” was achieved during the study described here. Of course, there is room for improvement with a higher resolution measurement. Regardless of the absolute measurement, the defective level was reduced to less than one thousandth of the starting level during this study. Several methods of defect reduction will be discussed. First, key philosophies of management will be explained. Next, several processes will be described which provided the framework for individual examples of improvement techniques. Ten specific improvement examples will be presented, each resulting in significant reductions in defects measured.

New Technique: Scanning Laser-SQUID Microscopy: A Novel Non-contact Electrical Inspection and Failure Analysis Technique

Abstract Scanning laser-SQUID microscopy is a new electrical inspection and failure analysis technique that can detect open, high-resistance, and shorted interconnects without electrical contact in areas ranging in size from a few square microns to an entire die. This article describes the setup of a prototype laser-SQUID system, explaining how it works and how it compares to other nondestructive defect localization techniques. It presents application examples in which laser-SQUID microscopy is used to locate gate oxide shorts to within 1.3 μm and detect IC defects prior to bond-pad pattering and after bonding and packaging. It also includes a series of images acquired from a board-mounted chip with fields of view ranging from 5 x 5 mm down to 50 x 50 μm.