Abstract
We propose a new method for SAT-based Boolean reasoning on multiple defects in digital ICs. Although it does not explicitly consider a specific fault model such as model-based techniques, it allows us to consider more realistic cases than model-free approaches. In particular, it can be used to account for (a) faults resulting in monotonic errors at the output of a cell and (b) faults, such as breaks or bridgings, that may corrupt the propagation of a signal from its fan-out branches. The model can be used for either standard gates or more complex combinational modules. Examples are shown for applications requiring the consideration of multiple defects such as fault diagnosis and reliability analysis. The feasibility of the proposed approach is assessed by results on a set of combinational benchmarks.
Highlights
Faults Affecting Logic Cells andThe expected reliability reduction [1,2] in digital FET-based nano-circuits will hardly be managed by the classical single-fault paradigm widely used in testing and in some fault-tolerant design techniques
The proposed approaches can be used to reason regarding several properties of digital
Starting from the netlist of each benchmark as it is described in BLIF [21], we have built the CNF of a miter featuring the conjunction of the fault-free CNF, the CNF describing the faulty circuit, and the CNF of a comparator fed by the primary outputs (POs)’ variables of the two copies of the circuit
Summary
The expected reliability reduction [1,2] in digital FET-based nano-circuits will hardly be managed by the classical single-fault paradigm widely used in testing and in some fault-tolerant design techniques. When analyzing the reliability of a circuit design, these techniques can be used to check whether multiple faults exist that produce output errors violating some required property In both cases, a huge set of additional variable assignments exists that satisfies the CNF of the circuit under diagnosis/reliability constraints. In [11], given a set of input assignments and output responses, a Quantified Boolean Formula (QBF) is built over the CNF describing the possible faulty circuits and it is solved under cardinality constraints In this context, we first compare model-based (considering stuck-at faults) approaches with model-free ones and we discuss their limitations. The proposed method is not applied here to a specific problem of testing, diagnosis or design of fault-tolerant circuits: we performed some experiments regarding the fault multiplicity with respect to output error cardinality in an attempt to produce worst-case conditions for the solver.
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