Defective Chips Research Articles

Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning

Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning

Similarity searching for wafer bin maps by measuring shape, location, and size similarities of defect patterns

A wafer bin map (WBM) is a visual representation of the spatial distribution of defective chips on a wafer. WBMs showing specific defect patterns are usually a result of process-assignable causes; thus, it is important to identify them to eliminate assignable causes. With advances in semiconductor manufacturing technology, identifying new defect patterns, and diagnosing their causes have become critical. However, most existing methods for WBM analysis use a supervised learning approach, which only detects previously known defect patterns. The similarity-search approach is a suitable alternative for defining new defect patterns. The proposed method uses an unsupervised approach to search for similar WBMs by measuring the similarities of three spatial features of defect patterns–shape, location, and size–which are useful for defining new defect patterns and diagnosing their causes. These three similarities are achieved using tensor voting and the mountain function for shape similarity, Euclidean distance for location similarity, and a combination of defect count and average radius for size similarity. The overall similarity was assessed using the weighted average of the three similarities. The weights are determined by quantifying the uncertainty of each similarity based on information entropy theory to better distinguish between similar patterns. The experimental results demonstrate the effectiveness of the proposed method compared to existing methods and highlight its capability to identify and describe the spatial features of defect patterns.

Chip-Level Defect Analysis with Virtual Bad Wafers Based on Huge Big Data Handling for Semiconductor Production

Semiconductors continue to shrink in die size because of benefits like cost savings, lower power consumption, and improved performance. However, this reduction leads to more defects due to increased inter-cell interference. Among the various defect types, customer-found defects are the most costly. Thus, finding the root cause of customer-found defects has become crucial to the quality of semiconductors. Traditional methods involve analyzing the pathways of many low-yield wafers. Yet, because of the extremely limited number of customer-found defects, obtaining significant results is difficult. After the products are provided to customers, they undergo rigorous testing and selection, leading to a very low defect rate. However, since the timing of defect occurrence varies depending on the environment in which the product is used, the quantity of defective samples is often quite small. Unfortunately, with such a low number of samples, typically 10 or fewer, it becomes impossible to investigate the root cause of wafer-level defects using conventional methods. This paper introduces a novel approach to finding the root cause of these rare defective chips for the first time in the semiconductor industry. Defective wafers are identified using rare customer-found chips and chip-level EDS (Electrical Die Sorting) data, and these newly identified defective wafers are termed vBADs (virtual bad wafers). The performance of root cause analysis is dramatically improved with vBADs. However, the chip-level analysis presented here demands substantial computing power. Therefore, MPP (Massive Parallel Processing) architecture is implemented and optimized to handle large volumes of chip-level data within a large architecture infrastructure that can manage big data. This allows for a chip-level defect analysis system that can recommend the relevant EDS test and identify the root cause in real time even with a single defective chip. The experimental results demonstrate that the proposed root cause search can reveal the hidden cause of a single defective chip by amplifying it with 90 vBADs, and system performance improves by a factor of 61.

Development of a spatial dimension-based taxonomy for classifying the defect patterns in a wafer bin map

A wafer bin map (WBM) represents the locational information of defective chips on the wafer. The spatial correlation of defects on the wafer provides crucial information for the root cause diagnosis of defects in wafer fabrication. The spatial correlation is classified as a defect pattern for efficient diagnostics. A defect pattern taxonomy should be defined in advance for coherent classification of defect patterns. Various taxonomies are used in previous studies, but they share common limitations in that the differentiation among defect patterns is unclear, the set of predefined defect patterns is insufficient, and they cannot accommodate newly-emerged defect patterns. A concept of spatial dimension-based defect pattern taxonomy and its development procedure are proposed. Defect patterns are defined by three spatial dimensions, namely, Shape, Size, and Location. The development procedure is applied to a major NAND flash memory semiconductor manufacturer for two years. Results show that spatial dimension-based taxonomy can improve the performance of the defect pattern classification system by alleviating common existing limitations. Moreover, meaningful defect patterns for diagnostics are retained through the engineers’ involvement in the development procedure.

Micro LED defect detection with self-attention mechanism-based neural network

We propose a method utilizing a YOLO detector for the precise localization of defective chips and the identification of defect types within multi-scale multi-target images. To address the challenge of optimizing training costs and enhancing model generalization, we introduce an end-to-end deep neural network, CM-YOLOv5, specifically designed for chip detection. We incorporate a novel bottleneck layer, MA-CSP, in conjunction with Multi-Head Self-Attention mechanism (MHSA). Additionally, we propose a class-balanced loss function (CB-BCE Loss) to tackle the issue of uneven distribution of defective samples in the Micro LED dataset. To further enhance convergence speed and detection precision, we introduce the SIoU Loss combined with Meta-AconC. Our experimental results, conducted on the Micro LED dataset, demonstrate notable improvements with CM-YOLOv5 over the basic YOLOv5 algorithm. Specifically, CM-YOLOv5 exhibits a 3.8 % increase in mean average precision and a 3.7 % improvement in precision, surpassing current mainstream object detection algorithms, including YOLOR, YOLOX, and YOLOv6, etc., in terms of general evaluation metrics. Finally, upon deploying our proposed algorithm on the edge device NVIDIA Jetson Xavier NX, CM-YOLOv5 demonstrates commendable speed and detection performance in embedded scenarios.

Industrial defective chips detection using deep convolutional neural network with inverse feature matching mechanism

Abstract The growing demand for high-quality industrial products has led to a significant emphasis on image anomaly detection (AD). AD in industrial goods presents a formidable research challenge that demands the application of sophisticated techniques to identify and address deviations from the expected norm accurately. Manufacturers increasingly recognize the significance of employing intelligent systems to detect flaws and defects in product parts. However, industrial settings pose several challenges: diverse categories, limited abnormal samples and vagueness. Hence, there is a growing demand for advanced image AD techniques within industrial product manufacturing. In this paper, an intelligent industrial defective chips detection framework is proposed which mainly consists of three core components. First, the convolutional features of the efficient backbone model is effectively utilized to balance the computational complexity and performance of industrial resource-constrained devices. Secondly, a novel inverse feature matching followed by masking method is proposed to enhance the explanability that localizes the abnormal regions of the abnormal chips. Finally, to evaluate our proposed method a comprehensive ablation study is conducted, where different machine learning and deep learning algorithms are analysed to claim the superiority of our method. Furthermore, to help the research community, a benchmark dataset is collected from real-world industry manufacturing for defective chip detection. The empirical results from the dataset demonstrate the strength and effectiveness of the proposed model compared to the other models.

Semi-Supervised Learning for Simultaneous Location Detection and Classification of Mixed-Type Defect Patterns in Wafer Bin Maps

Identifying the patterns of defective chips in wafer bin maps (WBMs) in semiconductor manufacturing processes is crucial because different defect patterns correspond to different root causes of process failures. Recently, mixed-type defect patterns (i.e., multiple defect patterns in a single wafer) have become increasingly common owing to the increased complexity of semiconductor manufacturing processes. Previous methods for classifying mixed-type defect patterns in WBMs focused on outputting only the class labels of the defect patterns and not their locations, although location information of the defect patterns is useful for tracking the root causes of failure and improving processes. Moreover, most previous methods used only labeled WBM data, although a larger quantity of unlabeled WBM data are more accessible because of the costly process of label annotation. Therefore, in this paper, we propose a semi-supervised learning method for classifying mixed-type defect patterns and detecting their locations simultaneously using both labeled and unlabeled WBM data. The proposed method extends a recent unsupervised object detection method called Attend-Infer-Repeat in a semi-supervised manner to perform object detection and classification simultaneously. The performance of the proposed method is verified using WBM datasets of different sizes. The results demonstrate the effectiveness of the proposed method for classification and location detection.

LED Chip Defect Detection Method Based on a Hybrid Algorithm

LED is an extremely important energy-saving lighting products, which has greatly facilitated human life. Meanwhile, it also makes a positive contribution to global carbon neutrality and carbon peaking. Defect detection is a vital part of the production process to control the quality of LED chips. The traditional methods use a microscope for manual visual inspection, which is time-consuming and has inconsistent testing standards, low efficiency, and other deficiencies. To solve these problems, a hybrid algorithm based on geometric computation and a convolutional neural network is proposed for LED chip defect detection. The method takes advantage of the dimensionality reduction of geometric computation to perform coarse detection of defects on preprocessed chip lithography graphs in the form of grid segmentation, which realizes fast coarse screening of large-scale chip samples and reduces postcomputational costs. The convolutional neural network model is used for the secondary fine detection of “suspected defective” chips after geometric coarse screening, and the SPP (spatial pyramid pooling) network model is improved by directly introducing the original feature map into the SPP pooling layer for summation to enhance the global and local feature information of the output feature map. Furthermore, we construct an LED chip image acquisition platform using a high-frequency multimagnification zoom lens, collect training samples of defective chips, and increase the number of samples through image processing techniques. The research introduces the R-CNN, SDD, and YOLO methods to evaluate the superiority of our method in a number of experiments. The experimental results show that our algorithm proposed in this paper has an average precision (AP) of 96.7% for large-scale chip detection with a low defect rate. Compared with other methods, the testing mean average precision (mAP) is 10.39% higher than traditional YOLO v2. The testing mIoU is also 3.63% higher than traditional YOLO v5, the detection speed is also significantly improved, and it has good robustness.

Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC’s

This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, bridges, void formation, thermal and physical stress, etc., during the TSV fabrication and stacking of 3D ICs. The repair mechanism provides a redundancy feature to replace the failing TSVs with spare TSVs in the design. It provides a significant impact on yield compared to the standard TSV testing approach. Further analysis was performed on different stacked levels of 3D ICs, and the results were compared with the existing industrial methods in terms of the yield and test time parameters. The proposed mechanism showed a significant improvement of 12.5% in the yield and 17.5% in the test time and also recovered all defective chips efficiently.

Semiconductor wafer defect classification using convolution neural network: a binary case

With the multitude of steps used in semiconductor industry, automation is being practiced extensively in its manufacturing processes to guarantee quality of manufactured chips and improvement in production. At front end of line, wafer are probed and defective chips are segregated. From this data wafer bin map are generated, these show defects on the surface of wafers. If analysis of wafer bin map is done manually, this may result in incorrect categorization of defects due to human error and lack of judgement. Thus, the rationale behind this research study is to determine the scope of vision-based methods for automatic classification of wafer defects. In view of this, a classifier which detects Type A and Type B defects in wafers is proposed. It involves a Convolution Neural Network (CNN) based binary classifier. 250 Images of each class of wafer bin map dataset, is used to conduct the study on five layer CNN architecture. The proposed setup gives the test accuracy of 97.7%.

Approximate TSV-based 3D Stacked Integrated Circuits by Inexact Interconnects

Three-Dimensional Stacked Integrated Circuit (3D-SICs) based on Through-Silicon Vias (TSVs) provide a high-density integration technology. However, integrating pre-tested dies requires post-bond interconnect testing, which is complex and costly. An imperfect TSV-based interconnect indicates a defective chip that should be rejected. Thus, it increases the yield loss and test cost. On the other hand, approximate computing (AC) is a promising design paradigm suitable for error-resilient applications, e.g., processing sensory-generated data, by judiciously sacrificing output accuracy. AC perform inexact operations and accepts inexact data. Thus, introducing AC into 3D-SICs will significantly ameliorate the efficiency of design approximation. Therefore, this work aims to increase the yield and reduce the test cost by accepting 3D-SICs with defected interconnects as approximate 3D-SICs. This work considers 3D-SICs, where the sensor is stacked on logic (CPU) which is stacked on memory (DRAM). Then, use the memory-based interconnect testing (MBIT) approach to detect and diagnose the faulty interconnect. Based on the detected fault location and type, and for a maximum allowed error, some sensory 3D-SICs with defected LSBs interconnects are accepted and used in error-resilient and data-intensive applications. Targeting data lines only, 50% of the defected interconnects, i.e., least significant bits (LSBs), were accepted as approximate. Thus, the proposed work was able to significantly increase the yield. Two applications, i.e., ECG signal compression and detecting of their R peaks,demonstrated the effectiveness of using a sensory device with a faulty data line in its least significant 8-bits. The approximate ECG signals have a compression rate higher than the exact with negligible (around 0.1%) reduced accuracy.

Prediction of highly imbalanced semiconductor chip-level defects using uncertainty-based adaptive margin learning

In semiconductor manufacturing, the package test is a process that verifies whether the product specifications are satisfied before the semiconductor products are finally shipped to customers. The packaged chips are classified as good or defective according to the verification results. To ensure high-quality products and customer satisfaction, it is important to detect defective chips during the package test. In this article, we consider the problem of predicting potential defects in advance using the wafer-test results data obtained from an earlier stage of the wafer test. There are several challenges in this problem. First, package-test data are highly class-imbalanced with a very low defect rate, and the imbalance level may vary due to the variability in manufacturing processes. Second, there is a complex relationship between package- and wafer-test results. Third, it is more important to increase the detection accuracy of defects than the overall classification accuracy. To address these challenges, we propose a Bayesian-neural-network-based prediction model. The proposed model adaptively considers unknown imbalance levels through the flexible adjustment of the decision boundary by using class- and sample-level prediction uncertainties and the relative frequency of each class. Using a real semiconductor manufacturing dataset from a global semiconductor company, we demonstrate that the proposed model can effectively predict defects even when the imbalance level of the test dataset differs from that of the training dataset.

An oversampling method for wafer map defect pattern classification considering small and imbalanced data

A wafer consists of several chips, and a wafer map shows the locations of defective chips on the wafer. The locational pattern of defective chips on the wafer map provides crucial information for improving the semiconductor wafer fabrication process. Recently, automatic defect pattern classification using convolutional neural networks (CNN) has become popular because of its good classification performance. The good performance is guaranteed only when a large amount of well-balanced training and test data is available. However, such data are difficult to obtain in real practice because the training and test data are obtained by manual inspection. In this paper, we propose a systematic method to resolve the small and imbalanced wafer map data issues. Specifically, we first selected wafers showing clear defect patterns and then replicated them by randomly applying horizontal flip, vertical flip, and rotation. In the case study, we obtained real wafer map data from a semiconductor wafer company. By applying the proposed method, a large amount of well-balanced data was obtained. The CNN model for defect classification was fitted to the obtained data, and it showed good classification performance.

A Graph-Theoretic Approach for Spatial Filtering and Its Impact on Mixed-Type Spatial Pattern Recognition in Wafer Bin Maps

Statistical quality control in semiconductor manufacturing hinges on effective diagnostics of wafer bin maps, wherein a key challenge is to detect how defective chips tend to spatially cluster on a wafer--a problem known as spatial pattern recognition. Recently, there has been a growing interest in mixed-type spatial pattern recognition--when multiple defect patterns, of different shapes, co-exist on the same wafer. Mixed-type spatial pattern recognition entails two central tasks: (1) spatial filtering, to distinguish systematic patterns from random noises; and (2) spatial clustering, to group filtered patterns into distinct defect types. Observing that spatial filtering is instrumental to high-quality mixed-type pattern recognition, we propose to use a graph-theoretic method, called adjacency-clustering, which leverages spatial dependence among adjacent defective chips to effectively filter the raw wafer maps. Tested on real-world data and compared against a state-of the-art approach, our proposed method achieves at least 46% gain in terms of internal cluster validation quality (i.e., validation without external class labels), and about ~5% gain in terms of Normalized Mutual Information--an external cluster validation metric based on external class labels. Interestingly, the margin of improvement appears to be a function of the pattern complexity, with larger gains achieved for more complex-shaped patterns.

Russian sawmill modernization (a case study). Part 2: improving the efficiency of wood chipping operations

ABSTRACT Given the upward trend of deforestation in the world, improving the quality of wood waste sorting operations is a major challenge in forestry from the perspective of energy saving and environmental conservation. The quality of wood chips defines their further application, whether it is production or fuel. The second case study presents a new approach to the problem of sorting wood chips for increasing their quality using machine learning and laser scanning technology. The proposed methodology includes functions to analyse the fractional size distribution among wood chips and rot detection. It shows that once a defective chip is detected, the quality control system will automatically remove it from the conveyor belt while it is moving. The minimization of wood waste will reduce logging intensity and increase the profitability of lumber enterprises.

A Unified Defect Pattern Analysis of Wafer Maps Using Density-Based Clustering

For a yield enhancement in semiconductor manufacturing, it is necessary to analyze wafer maps since they contain information gathered during the manufacturing such as test results of each chip. Especially, spatial patterns of defective chips, e.g. zone, scratch, ring patterns, etc. presented on a wafer map provide valuable information on the potential causes of malfunctions in a fabrication process. Numerous automatic analysis methods have been developed for identifying such defect patterns. We propose a defect pattern analysis method based on density-based clustering (DBC), which consists of two steps: conducting a statistical test to detect wafer maps that contain abnormal defects and clustering the defect patterns. Specifically, we develop a new statistic based on the core points from DBC for the spatial randomness test, which requires much fewer examinations to identify abnormal wafer maps than the existing joint-count based statistics. With those core points, clustering of abnormal defects can be coherently performed in the subsequent clustering step. The main advantage of our method over previous automatic detection methods is that it performs both steps simultaneously based on the core points from DBC. The proposed method is evaluated on simulated and real wafer map datasets. Experimental results show that the proposed method identifies spatial dependence among defects as accurate as the existing methods, but with much less computational effort.

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

Stable and Efficient Transfer-Printing of GaN-Based Microscale Light-Emitting Diode Array for Deformable Displays

GaN-based microscale light-emitting diodes (μLEDs) are reported for assembly into deformable displays and repair systems. A stamp-imprinting method that enables large area assembly without spatial limitation is involved in the system, and a selective pick-up method is presented that includes a method for removing detected defective chips through micro-pulsed laser scanning. The photosensitive functional material, which is an accepted layer for the stable imprinting of chips, is determined by controlling the adhesion. In addition, selective pick-up and adhesion-controlled functional materials allow the implementation of defect-free displays through two pick-and-place cycles. Displays and related systems fabricated with this method can offer interesting optical and electrical properties. Figure 1

Improving Compression Ratios for Code-Based Test Pattern Compressions through Column-Wise Reordering Algorithms

Chip testing is an effective way to reduce the number of defective or faulty chips that reach the market. However, as large-scale test patterns need to be transmitted into a circuit under test during testing, the transmission time dominates the test application time of the chip testing. Therefore, code-based compression methods are widely used in compressing test patterns because of their capability to reduce the transmission time and save storage space significantly. Current code-based compression methods cannot fully apply the inherent characteristics of test patterns yet. To address this problem, this study proposes two-stage test pattern preprocessing algorithms, thereby improving the efficiency of the code-based compression method. First, we propose a column-wise reordering for Hadamard matrix (CRHM) algorithm, which decomposes a test set consisting of test patterns into a primary component set (PCS) and a residual component set (RCS). The PCS inherits some 1s from the original test set (OTS), and other 1s belong to the RCS. As the number of 1s contained in the RCS is less than that in the OTS, the RCS can obtain a higher code-based compression ratio. The PCS can be generated by an on-chip generator, which does not consume transmission time. Second, we propose a novel column-wise reordering for the RCS (CRRCS) algorithm. The CRRCS solves the new location of each column of the RCS one by one in the list to decrease the entropy of the RCS. The entropy denotes the shortest length of the codeword required for the symbol to be encoded. The smaller entropy value refers to a higher compression ratio. For the sorted RCS, more high-frequency symbols can be replaced by shorter codewords. Experimental results based on seven code-based compression methods show that the proposed algorithms can increase the average compression ratio by a total of 19.91%, and the highest average compression ratio reaches 85.04% for ISCAS’89 benchmark circuits.

Fully convolutional networks for chip-wise defect detection employing photoluminescence images

Efficient quality control is inevitable in the manufacturing of light-emitting diodes (LEDs). Because defective LED chips may be traced back to different causes, a time and cost-intensive electrical and optical contact measurement is employed. Fast photoluminescence measurements, on the other hand, are commonly used to detect wafer separation damages but also hold the potential to enable an efficient detection of all kinds of defective LED chips. On a photoluminescence image, every pixel corresponds to an LED chip’s brightness after photoexcitation, revealing performance information. But due to unevenly distributed brightness values and varying defect patterns, photoluminescence images are not yet employed for a comprehensive defect detection. In this work, we show that fully convolutional networks can be used for chip-wise defect detection, trained on a small data-set of photoluminescence images. Pixel-wise labels allow us to classify each and every chip as defective or not. Being measurement-based, labels are easy to procure and our experiments show that existing discrepancies between training images and labels do not hinder network training. Using weighted loss calculation, we were able to equalize our highly unbalanced class categories. Due to the consistent use of skip connections and residual shortcuts, our network is able to predict a variety of structures, from extensive defect clusters up to single defective LED chips.