Abstract
Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.
Highlights
The hardware/software co-simulation of complex systems on a chip from the early stages of design have an essential role since it allows us to reduce the time to market for the final product
The technological evolutions in the research and development of multiprocessor systems on chip (MPSoC), show that these systems have a high computing capacity, the architecture which remains the most evolving for this kind of capability is Distributed shared memory (DSM), since it combines the advantage of two types of systems
The results clearly show that the speed of execution on the PVT level is significant, the speed at the transaction level modeling (TLM) sub-level is more important than that on the CABA level, the results show the impact of the number of processors which decreases the execution time with the increase in the number of processor
Summary
The hardware/software co-simulation of complex systems on a chip from the early stages of design have an essential role since it allows us to reduce the time to market for the final product. For this reason, this cosimulation imposed the presence of tools to make powerful, accurate, and rapid development. This cosimulation imposed the presence of tools to make powerful, accurate, and rapid development The technological evolutions in the research and development of multiprocessor systems on chip (MPSoC), show that these systems have a high computing capacity, the architecture which remains the most evolving for this kind of capability is Distributed shared memory (DSM), since it combines the advantage of two types of systems.
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