Defect Etching Research Articles

Low-temperature annealing of (Hg,Cd)Te

Many methods for the employment of (Hg,Cd)Te alloys employ anneals at temperatures <300°C to convert the p type left over from the growth process or to adjust the concentration of the native acceptors. An investigation of the kinetics of this annealing process has been performed as functions of (1) vacancy concentration; (2) composition, or the CdTe mole fraction in the alloy; and (3) temperature. If these anneals are carried out under mercury-saturated conditions, the tellurium precipitates in the material, which result either from the growth process or from specific thermal histories, are annihilated by in-diffusing mercury, which results in a significant multiplication of dislocations. This interface, delineated by defect etching, has been employed to investigate the kinetics of the annealing process. These results will be unaffected by the uncertainties introduced in determining this interface by electrical measurements, which arise from incomplete ionizations of the metal vacancies at 77 K for Hg1−xCdxTe with CdTe mole fractions exceeding ∼0.26. The annealing rate appears to be strongly dependent on both the temperature and composition of the alloy, decreasing with increasing CdTe mole fraction, within 0.15 and 0.5, with the behavior resembling a composition-dependent, activated-diffusion process. The depth of the interface appears to vary inversely as the root of the metal-vacancy concentration.

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The <110> substrate is used for HCBT fabrication utilizing <111> crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.

TEM investigation of defect reduction and etch pit formation in GaN

ABSTRACTGaN samples of this study were chemically wet etched to gain easier access to the dislocation sturcture. The scanning electron microscopy and transmission electron microscopy investigations revealed four different types of etch pits. After brief etching, several dislocations with screw component showed large etch pits, which may be correlated with the core of the screw dislocation. By means of SiNx micromasking the dislocation density could be reduced by more than one order of magnitude. The reduction of threading dislocations in the SiNx region in GaN grown on 〈0001〉 sapphire is due to bending of the threading dislocations into the {0001} plane, such that they form dislocation loops if they meet dislocations with opposite Burgers vectors. Accordingly, the achievable reduction of the dislocation density is limited by the probability that these dislocations interact. Edge dislocations bend more easily on account of their low line tension. This results in a preferential bending and reduction of dislocations with edge character.

A new preferential etch of silicon ( [formula omitted]) with ammonia system

Preferential etching is a simple and fast technique to evaluate the structural perfection of a simple crystal. For silicon crystals, this technique is widely used to delineate crystal defects generated during crystal growth, wafer preparation and processing. An investigation of the NH 4OH–CH 3COOH system shows that preferential etching of crystal defects on (1 1 1) silicon surface is very sensitive to the concentration ratio of NH 4OH and CH 3COOH. The investigation of this system leads to development of an improved etch. This etch consists of 80–90 parts of NH 4OH and 20–10 parts of CH 3COOH. The newly developed etch can delineate a wide variety of crystal defects with sharp definition, high resolution and minimum surface roughness, over a range of resistivities. A slow etch rate (0.35 μm/min) at 75 °C provides etch control. In most cases, the etch time required is about 15 min.

High Ge content photodetectors on thin SiGe buffers

PIN SiGe photodetectors (PD) are grown by MBE with Ge contents x=0, 0.10, 0.2, 0.27 and 0.5. For PDs with high Ge content, which are grown beyond the SiGe layer critical thickness, thin (sub 100 nm) strain relaxed, p +(B)-doped SiGe buffers are of special importance. The layer structure of the samples consists of a 5×10 18 cm −3 p +(B)-doped buffer layer as a bottom contact, followed by a 300 nm intrinsic active zone covered with a 3×10 20 cm −3 n ++(Sb)-doped top contact layer. Extremely low temperatures (LT) during the first growth stage of the SiGe buffers are implemented. Process windows for high strain relaxation on different substrates are determined. The role of growth conditions in crystal structure formation is in situ monitored by time resolved reflectivity (TRR) measurements. For comparison, pseudomorphic PDs and that on conventional graded buffers were also realised. Secondary ion mass spectrometry (SIMS), μ-Raman-spectroscopy and energy dispersive X-ray (EDX) analysis are performed to measure Ge content, composition profiles and degree of relaxation. The microstructure is characterised by cross-section transmission electron microscopy (XTEM). By optical microscopy with Nomarski differential interference contrast (NIC) combined with defect etching technique, typical defects in the layers were studied. Electrical measurements are performed to determine the different current components. The DC current–voltage characteristics show a distinct diode ‘s behaviour of the detectors, which are optically characterised in terms of reverse current for different incident wavelengths.

Screening the High-k Layer Quality by Means of Open Circuit Potential Analysis and Wet Chemical Etching

ABSTRACTA fast way to monitor the quality of high-k dielectric layers is wet etching, either monitored by Open Circuit Potential analysis or by Scanning Electron Microscopy. Defect densities in the order of 1.109 defects/cm2 are observed for as-deposited HfO2 layers. It is assumed that the mechanism for wet chemical defect observation is either due to crystallization and/or due to an oxygen deficient HfO2 layer resulting in Si/SiO up-diffusion upon thermal treatment. However, after appropriate post deposition annealing wet etch defect free layers can be prepared.

Surface and bulk characterization of thermally induced defects during silicon single wafer epitaxy

We investigated the generation and characterization of thermally induced defects during silicon epitaxy. To induce thermal slip into test wafers, steep radial and axial temperature gradients were introduced in 150 mm diameter test wafers during the temperature ramp-up in a single wafer reactor. Epitaxial layers were deposited by vapor phase epitaxy at ∼1100°C using trichlorosilane as a precursor gas. The wafers were characterized using laser light scatter surface maps, atomic force microscopy, X-ray diffraction, double crystal X-ray topography, and defect etching. Dislocations and stacking faults in densities of up to 5×10 7 cm −2 were found inside a distinct ring-shaped pattern on the wafer surface, compared to significantly lower densities (∼10 2 cm −2) outside of the ring pattern region. The distribution of the observed surface light scatter points at the epitaxial layer surface corresponds to the ring-shaped region of thermal slip. In certain cases, the hillocks were not detected using commonly employed detection methods like laser light scattering. We attribute the surface features to the deposition parameters employed. The detection capability for encountered defects is discussed in this paper.

Measuring the implantation depth of silver clusters in graphite

Scanning tunnelling microscopy (STM) and molecular dynamics (MD) simulations have been used to investigate the implantation of Ag7- clusters into the graphite surface. An experimental measure of the implantation depth of individual clusters is gained via thermal oxidation of the bombarded graphite surfaces. This process results in etching of the cluster-induced defects to form etch pits which grow laterally whilst retaining the depth of the implanted cluster. STM imaging of the etch pits reveals the distribution of implantation depths for deposition energies of 2 keV and 5 keV. Molecular dynamics simulations for clusters of 5 keV energy show that the implantation depth for Ag7- is largely independent of the impact site on the graphite surface and the cluster orientation. The implantation depth found by MD lies at the upper edge of the experimental depth distribution.

Observation of etch pits and defects in diamond single crystals prepared under high temperature–high pressure

As-grown diamond single crystals synthesized under high temperature–high pressure in the presence of FeNi catalyst were directly observed by scanning electron microscopy and transmission electron microscopy (TEM). Etch pits on the (1 1 1) surface of the diamond, which are generated by the screw dislocations meeting the diamond (1 1 1) surface at the points of emergence of dislocations, can be revealed by electrolytic etching and be used to study the motion of dislocations under the action of applied stress. Stacking-fault tetrahedral and stacking faults were investigated by moiré images. The stacking-fault tetrahedral and stacking faults may be derived from supersaturated vacancies generated during rapid cooling from high temperature to room temperature. Dislocation networks and an array of parallel dislocations were directly examined by TEM, which are related to the thermal stress caused by the inclusions in the diamond.

Photoluminescence study of a bulk vapour grown CdTe crystal

Low-temperature photoluminescence has been used to profile the distribution of impurities and defects through a CdTe boule grown at 700°C by the new “multi-tube” vapour-growth technique. The PL spectrum is dominated by an acceptor bound exciton band at 1.590 eV. We also observe eA 0 and DAP recombination. The Y luminescence band at 1.477 eV is also present and there are no other deep level bands observed. The identification of the luminescence bands is confirmed by temperature and intensity-dependent measurements and also by the strength of the phonon coupling. The PL data is used to map out the distribution of impurities and dislocations throughout the boule and supports previously published X-ray and defect etching data.

Erosion of steel under bombardment with ions of a deuterium plasma

The processes of sputtering of austenitic stainless steel (similar to 316SS) under long-term bombardment with ions of deuterium plasma (energy 0.1–1.5 keV) as well as effects of erosion on optical properties of steel surface are investigated. It was found that for this kind of material there is no selective etching of crystallographic defects that come out to the surface; therefore the rate of reflectance degradation decreases. Investigation of the optical properties of the surface subjected to ion bombardment requires taking into account not only the development of surface microrelief but also radiation damage created in the near-surface layer.

Molecular beam epitaxial growth of HgCdTe on CdZnTe(311)B

A series of n-type, indium-doped Hg1−xCdxTe (x∼0.225) layers were grown on Cd0.96Zn0.04Te(311)B substrates by molecular beam epitaxy (MBE). The Cd0.96Zn0.04Te(311)B substrates (2 cm × 3 cm) were prepared in this laboratory by the horizontal Bridgman method using double-zone-refined 6N source materials. The Hg1−xCdxTe(311)B epitaxial films were examined by optical microscopy, defect etching, and Hall measurements. Preliminary results indicate that the n-type Hg1−xCdxTe(311)B and Hg1−xCdxTe(211)B films (x ∼ 0.225) grown by MBE have comparable morphological, structural, and electrical quality, with the best 77 K Hall mobility being 112,000 cm2/V·sec at carrier concentration of 1.9×10+15 cm−3.

Fast Deposition Process for Graded SiGe Buffer Layers

Low-energy plasma-enhanced chemical vapour deposition (LEPECVD) is shown to allow for the synthesis of relaxed graded Si1-xGex, (0≤x≤1) buffer layers at deposition rates above 5 nm/s. On the basis of X-ray reciprocal space mapping, transmission electron microscopy, atomic force microscopy and defect etching, the quality of these buffer layers is shown to be comparable to similar structures grown by other techniques at much lower rates. LEPECVD and molecular beam epitaxy (MBE) have been combined for the synthesis of modulation-doped Si quantum wells, yielding mobilities up to 150000 cm2/Vs at 2 K.

Strain relaxation of graded SiGe buffers grown at very high rates

The strain relaxation in compositionally graded SiGe alloy buffers was studied as a function of growth temperature and growth rate. We have used a plasma enhanced CVD technique that we call low energy plasma enhanced chemical vapour deposition (LEPECVD) to access growth rates in the range of 0.9–3.8 nm/s at substrate temperatures between 640 and 725°C. The samples were analysed by X-ray reciprocal space mapping, transmission electron microscopy and defect etching. Despite the very high growth rate, the structural properties of the buffers are identical to buffers grown at rates one or two orders of magnitude lower. The threading dislocation density is shown to decrease significantly with increasing temperature in the investigated range.

渦電流探傷プローブを用いた欠陥形状による検出信号特性

Eddy-current testing (ECT) is a non-destructive inspection method having various advantages, such as testing that involves both conduction and non-contact. One attractive application for ECT is inspection for etching defects in high-density printed-circuit boards (PCBs). To apply the ECT technique to PCBs, it is important not only to make a conformable probe but also to investigate the characteristics of signals using the probe to determine the shapes of defects. This paper describes characteristics of inspecting signals for shapes of defects. When resultant signals are expressed in two dimensions, we can clearly examine etching defects in PCBs.

X-cut miniature tuning forks realized by ion track lithography

With the recently developed ion track lithography based on the selective etching, widening, and merging of ion-induced defects collectively resembling a superimposed anisotropy in certain areas as defined by a stencil mask, 39-kHz x-cut miniature tuning forks with a tine size of 331x2, 500x42 mum and a Q-value of up to 42 000 were fabricated from single crystalline quartz mostly to demonstrate this new technique's ability to structure difficult cuts, but also to benefit from the much simpler electrode configuration possible with this cut in comparison with ordinary z-cut watch tuning forks.

The effect of as-implanted damage on the microstructure of threading dislocations in MeV implanted silicon

The dose dependence of as-implanted damage and the density of threading dislocations formed after MeV implants into Si is measured. The role of the damage and amorphization in the evolution of dislocation microstructure is assessed. As-implanted damage is analyzed by Rutherford backscattering spectroscopy and channeling. Defect etching is used to delineate threading dislocations in near-surface regions of annealed (900 °C, 30 min) samples. For a variety of implants with 1.1 μm projected range (600 keV B, 1 MeV P, and 2 MeV As) we observe a sharp onset for formation of threading dislocations with a peak in dislocation density at a dose of about 1×1014 cm−2, this dose depends on the ion mass. With a further increase in dose, the dislocation density decreases. This decrease, however, is drastically different for the different ions: sharp (4–5 orders of magnitude) reduction for P and As implants and slow decline for B implant. The sharp decrease in the density of threading dislocations at higher doses is correlated with the onset of amorphization observed by channeling for P and As implants. Our data for low-temperature implants provide conclusive proof that a reduction in the dislocation density for P and As implants is a result of amorphization.

Excess low frequency noise/I-V studies in p-on-n MBE LWIR Hg1−xCdxTe detectors

Excess low frequency noise is investigated for the first time in infrared MBE grown LWIR Hg1−xCdxTe double layer planar heterostructure (DLPH) detectors grown on lattice matched substrates. LWIR detectors having R0Aopt values at 40K in the 101–107 Θ-cm2 range have been characterized as a function of temperature between 120 and 20K. Detectors with R0Aopt≥103Θ-cm2 at 40K have theoretical diffusion limited performance down to 78K and detectors with R0Aopt ≥105 Θ-cm2 at 40K are within a factor of two of theoretical diffusion limited performance for T>65K. Activation energies extracted from noise (Vd=−100 mV) and dark current (Vd=−100 mV) vs temperature measurements were detector dependent. The activation energy for detectors with R0Aopt≈106 Θ-cm2 at 40K is ∼0.90*Eg to 0.99*Eg. The noise measured between 78 and 105K in the intermediate performance (R0Aopt∼103–104 Θ-cm2 at 40K) detectors are higher than the noise measured in the higher performance (R0Aopt∼105–107 Θ-cm2) detectors. In addition, the excess low frequency noise and the dark current at −100 mV in the intermediate and poor (R0Aopt∼101 Θ-cm2) performance detectors are temperature independent. For each detector measured, the activation energy extracted from noise (Vd=−100 mV) vs temperature measurements is equal to the activation energy extracted from the total dark current (Vd=−100 mV) vs temperature measurements. For different dark current mechanisms, the excess low frequency noise varies with temperature and also with area within statistical accuracy in the same manner as the total dark current through the detector. At 78K, the Tobin14 expression holds in the general sense for equal area detectors dominated by different current mechanisms and also for detectors with a wide range of implant dimensions (Aimp=3.85×10−7 cm2 to Aimp=6.25×10−4 cm2). Following measurements, the detectors were stripped of the passivation and overlaying metal layers and dressed by a defect etch to reveal defects in each detector. A correlation among noise, leakage current and defect type has been determined for each detector.

Crystallographic defects in thermally oxidized wafer bonded silicon on insulator (SOI) substrates

The crystalline quality of wafer bonded (WB) silicon on insulator (SOI) structures thermal treated in dry oxygen ambients has been investigated by means of transmission electron microscopy and defect etching. The main crystallographic defects present in the SOI layers are dislocations, amorphous precipitates, and oxidation induced stacking faults (OISF). The evolution of the OISFs with time and temperature has also been investigated. The main feature observed is that the OISF in WB SOI structures undergo a retrogrowth process at temperatures around T = 1195°C for times of t = 2h. This result is very similar to that recently reported for oxygen implanted SOI (SIMOX) but considerably different from that observed in bulk silicon. The experimental data fits nicely a model recently proposed for the retrogrowth of OISF in thin SOI layers. This model considers that the self-interstitial supersaturation is considerably reduced compared to bulk silicon due to the relative fast point defect recombination inside the top silicon layer.

Thermal stability of Si/Si1−x−yGexCy/Si quantum wells grown by rapid thermal chemical vapor deposition

The thermal stability of Si/Si1−x−yGexCy/Si quantum wells was studied by high resolution x-ray diffraction, Fourier transform infrared spectroscopy, and defect etching. There are different pathways of strain relaxation in this material system, depending on the annealing temperature. The lattice structure of Si1−x−yGexCy was as stable as the Si1−xGex alloys at an annealing temperature of 800 °C for 2 h. At an annealing temperature of 900 °C for 2 h, the structures of both Si1−x−yGexCy and Si1−xGex started to relax. The addition of C enhanced the Ge outdiffusion in Si1−x−yGexCy, compared to that of Si1−xGex. For the annealing temperatures of 950 and 1000 °C for 2 h, the Si1−xGex continued to relax with the decrease of strain in the quantum wells, but the Si1−x−yGexCy relaxed with the increase of the strain due to the formation of SiC precipitates. Misfit dislocation formation was observed in the Si1−x−yGexCy alloys with initial thicknesses below the critical thickness after annealing at 1000 °C for 2 h. This relaxation is probably caused by the SiC precipitation, since SiC precipitates can reduce the strain compensation and, therefore, decrease the critical thickness.