Deep-submicron CMOS Processes Research Articles

Composite Gate Oxide Method for Improving the Reliability and Leakage Performance of Deep Submicron CMOS Processes

This article aims to address the issues of gate oxide reliability failure and leakage loss in SRAM circuits caused by the introduction of additional high-voltage devices in the 90 nm standard process. It investigates the corner thinning phenomenon using different gate oxide scheme. It analyzes the corresponding relationship between composite gate oxide and reliability and tests the leakage of the SRAM circuit. Research has shown that the use of composite gate oxide can effectively improve corner thinning. The ratio of thermal oxide to HTO in composite gate oxide directly affects GOI/TDDB. At the same time, the use of composite gate oxide also decreases device leakage to a certain extent. The standby leakage of SRAM circuits(Isb) can be reduced from 200 nA to less than 10 nA.

An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders

SummaryThe sharp increase in the leakage part of the total power of the very large scale integration (VLSI) circuits is a significant concern in the deep submicron CMOS process. The NOT gates, Gate Diffusion Input (GDI) cells, restorer NMOS–PMOS transistors for full‐swing operation, and any path from the power voltage to the ground are the main sources of leakage power dissipation as well as short‐circuit in the VLSI CMOS circuits/chips. The input controlled leakage restrainer transistor (ICLRT) is a new circuit‐level method that is proposed in this paper. The ICLRTs can be deliberately added to any VLSI CMOS circuit to largely diminish the total power dissipation especially by the reduction of its leakage and short‐circuit parts. The full adders are vital parts in various VLSI circuits/systems, especially in circuits used for fulfilling arithmetic operations. Those are often placed in the critical paths for multiplication and division, so influence the throughout the efficiency of the system. To test the proposed technique, ICLRTs added to five best 1‐bit hybrid full adders in the deep submicron process to fit the needs of the day. The efficiency of the proposed method is evaluated using SPICE simulations in 22‐nm CMOS BSIM4 process. Evaluation outcomes with 1‐V power supply verified that the power dissipation and power‐delay product (PDP) of the hybrid full adders based on ICLRT technique relative to corresponding original designs are reduced 65.67–95.7% and 35.85–87.37%, respectively. Mismatch analysis and Monte Carlo simulations prove the robustness and stability of the presented circuits in the presence of the process, voltage, and temperature (PVT) variations.

TCAD tools in undergraduate studies: A laboratory work for learning deep submicron CMOS processes

This article discusses one exemplary and one original laboratory work from the micro- and nano-electronics manufacturing process laboratory works cycle. These laboratory works have been successfully introduced into the undergraduate programme and have been attended by students for several years at Vilnius Gediminas Technical University, Faculty of Electronics. This laboratory work is unique in that it consistently displays and graphically depicts practically all CMOS transistor manufacturing processes: from the preparation of the silicon wafer to the final passivation. Silvaco TCAD tools are used in order to simulate these technological processes. This type of laboratory works provides students with the necessary knowledge of chip manufacturing processes and TCAD tools without the use of costly manufacturing equipment specific to each technological process in the fabrication chain, long-term experiments and a large amount of human resources. This article also presents and discusses student feedback statistics over several years of studies, the advantages of this laboratory work, recommendations for further improvement and formulates conclusions.

A macro model of RF Schottky diode in 22-nm CMOS and its application

RF Schottky Barrier Diode (SBD) device can be compatible with deep submicron CMOS process, which is a research edge-cutting technology in the field of microelectronics. An accurate device model is highly required by the relevant circuit simulation work. In this paper, a macro device model of SBD in 22 nm CMOS node is developed based on the actual device structure. To increase its accuracy, a novel iterative algorithm is employed during the model parameter extraction. The simulation results are consistent with experimental data in frequency range from 10 MHz to 10 GHz, indicating that the developed SBD model can accurately reflect the DC and RF characteristics of the 22 nm device. Moreover, the application of the developed RF SBD device model is verified based on RF energy harvesting circuit in terms of the output voltage and efficiency, showing the feasibility of the developed SBD model in RF integrated circuit.

Parametric Study of p-n Junctions and Structures for CMOS-Integrated Single-Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) have emerged as the primary solid-state photodetectors for use in time-resolved imaging and very low light optical detection for their high sensitivity, fast impulse response, and CMOS process compatibility. For each application, diode structure and size must be optimized empirically, where device performance is difficult to predict theoretically. To assist in this iterative design process, this paper presents side-by-side characterization of multiple SPAD structures implemented using different p-n junctions in a single, deep sub-micron CMOS process. Detailed characterization of the sensors enables comparative analysis of important performance parameters, such as dark count rate and spectral response, across multiple p-n junction types, device structures, and SPAD size variants. A new approach for experimental analysis of after-pulsing is also presented. The characterized SPAD test array comprises multiple size and structural variants implemented in a general purpose 180nm CMOS process.

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links.

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM's Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software.

Use It or Lose It

Moore's Law scaling continues to yield higher transistor density with each succeeding process generation, leading to today's many-core chip multiprocessors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep submicron CMOS process technology is marred by increasing susceptibility to wear. Prolonged operational stress gives rise to accelerated wearout and failure due to several physical failure mechanisms, including hot-carrier injection (HCI) and negative-bias temperature instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic, a single fault in the interprocessor network-on-chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this article, we study HCI- and NBTI-induced wear due to actual stresses caused by real workloads, applied onto the interconnect microarchitecture and develop a critical path model for NBTI-induced wearout. A key finding of this modeling is that, counter to prevailing wisdom, wearout in the CMP's on-chip interconnect is correlated with lack of load observed in the NoC routers rather than high load. We then develop a novel wearout-decelerating scheme in which routers under low load have their wear-sensitive components exercised without significantly impacting cycle time, pipeline depth, area, or power consumption of the overall router. A novel deterministic approach is proposed for the generation of appropriate exercise-mode data, ensuring design parameter targets are met. We subsequently show that the proposed design yields an ∼2,300× decrease in the rate of wear.

A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator

In this paper, a time-domain high-order ΔΣ analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order ΔΣ ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.

Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS

This paper describes design considerations for a digital inductive-switching DC/DC converter suitable for direct battery connection in a deep sub-micron CMOS process. Digital control techniques and robust circuit design methods take advantage of the advanced process technology while avoiding the barriers to direct battery connection and high efficiency, high power density voltage conversion. The approach is verified on a prototype converter, implemented in 40 nm standard bulk CMOS. The design achieves a peak efficiency of 95% for an input range of up to 5.5 V. The transient response is optimized for typical mobile SoC operating conditions and achieves step response times as fast as 35 μs/V under load.

Recent progress in the development of 3D deep n-well CMOS MAPS

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

Direct detection in Transmission Electron Microscopy with a [formula omitted] pitch CMOS pixel sensor

This paper presents the characterization of a CMOS monolithic pixel sensor prototype optimized for direct detection in Transmission Electron Microscopy (TEM). The sensor was manufactured in a deep-submicron commercial CMOS process and features pixels of 5 μ m pitch. Different pixel architectures have been implemented in the test chip, and the best performing architecture has been selected from a series of tests performed with 300 keV electrons. Irradiation tests to high electron doses have also been performed in order to estimate device lifetime.

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp

Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.

A novel CMOS process compatible high performance parallel-stacked RF spiral inductor

In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications.

Design and Performance of a DNW CMOS Active Pixel Sensor for the ILC Vertex Detector

The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. The chip has been designed in a 130 nm triple-well CMOS process and fabricated by STMicroelectronics. This first prototype includes a 16 times 16 DNW-MAPS matrix with sparsified readout architecture, an 8 times 8 matrix with digital output and selectable access to the analog output in each cell, and a 3 t 3 matrix with all the analog outputs available at the same time. The analog front-end has been characterized and the digital readout circuits have been successfully tested at frequencies up to 50 MHz. The circuit design and the performance of SDR0 are discussed in this paper.

First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source ( 55 Fe ) tests, will be presented.

Design and fabrication of the suspended high-Q spiral inductors with X-beams

In this paper, deep sub-micron CMOS process compatible high Q on-chip spiral inductors with air gap structure were designed and fabricated. In the design the electromagnetic solver, SONNET, and the finite element program, ANSYS, were used for electrical-characteristics and maximum mechanical strength, respectively. The copper wires were capped with electroless Ni plating to prevent the copper from oxidizing. A Si3N4/SiO2 X-beam was designed to increase the mechanical strength of the inductor in air gap. The enhancement of maximum mechanical strength of a spiral inductor with X-beams is more than 4,500 times. Among these structures, the measured maximum quality factor (Q) of the suspending inductor and frequency at maximum Q are improved from 5.2 and 1.6 GHz of conventional spiral inductor to 7.3 and 2.1 GHz, respectively.

A 10-bit 205-MS/s 1.0-$\hbox{mm}^{2}$ 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm2 in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-VPP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.

Recent developments in 130 nm CMOS monolithic active pixel detectors

We developed monolithic active pixel detectors, by exploiting the triple well option available in a deep-submicron CMOS process. The novel features are the full analog signal processing and digital functionality implemented at the pixel level. The charge collecting element is realized using the deep N-well (DNW), the full in-pixel signal processing chain includes charge preamplifier, shaper, discriminator and latch. We report on the characterization of the two prototype chips, the first (APSEL0) containing single-channel sensors, with different collecting electrode area, and the latter (APSEL1) with several single pixel structures with improved noise figure implementing also an 8 × 8 matrix of 50 × 50 μm 2 pixel area. So far, the pixel matrix has a simple row by row readout, successfully tested with clock frequency up to 30 MHz. The response of the sensors to infra-red laser, β -rays and soft X-rays (from radioactive sources, 90 Sr and 55 Fe respectively) will be presented. The results achieved so far demonstrate the viability of the technology and suggest new design improvements implemented in the next prototype chips submission (APSEL2).

Recent progress in the development of a monolithic active pixel detector for a B factory

Monolithic Active Pixel Sensors (MAPS) may become the building blocks of vertex detectors at future high luminosity e + e - colliders. Requiring an active layer only a few tens of microns thick, MAPS can be thinned to ∼ 50 μ m , which reduces the multiple scattering of primary particles. Deep sub-micron CMOS processes allow for small pixel size, needed for adequate single point resolution and low occupancy at a Super B factory. Major concerns with MAPS are readout speed and signal stability for large pixel arrays. Laser bench test results of a full size prototype (CAP3) with 118,784 readout pixels and a 5-deep correlated double sampling pipeline are presented. Lessons learned are applied to a design iteration and investigation of two new digital readout sensor designs, all included in the CAP4 prototype chip.