Deep Etching Process Research Articles

Fabrication and stress analysis of annular-trench-isolated TSV

The large mismatches among the coefficients of thermal expansion (CTE) of the metal via, insulator liner, and Si substrate of the through-silicon via (TSV) induce thermal stresses within and around the TSV during thermal-cycled fabrication processes. Reduction of thermal stress in the Si substrate is important for minimizing the deviations in the device characteristics. An annular-trench-isolated (ATI) structure was proposed for the TSV to solve the thermal issues, which occur during the three-dimensional (3D) integrated circuit (IC) integration, by stress redistribution. The concept of ATI TSV is based on retaining a Si-ring between the metal core and insulator layer during the fabrication process. We realized the ATI TSV using a via-last fabrication approach, with two deep silicon etching processes (Bosch processes) for the insulator layer and the metal core. Parylene-HT was utilized as the insulator to achieve high uniformity. With a vacuum-assisted filling system, the vias were filled with a solder material. ATI TSVs with diameters of 10μm and 2-μm-thick Parylene-HT insulation layers were demonstrated. Studies on the thermal stress levels of the ATI TSV were carried out by finite-element method (FEM) simulation, along with comparisons with regular and annular TSVs. We revealed that the ATI TSV shows lower thermal stresses in the Si substrate than the regular and annular TSVs. The ATI TSV is a possible candidate for 3D IC integration with stress-sensitive devices.

A Multistep DRIE Process for Complex Terahertz Waveguide Components

A silicon deep reactive-ion etching (DRIE) process has been developed, using multiple SiO2 masks to enable multidepth waveguide features with ±2% tolerance. The unique capability of this process is demonstrated by designing, fabricating, and testing an orthomode transducer working in the 500–600 GHz frequency range. Straight waveguide measurements are also performed to characterize the losses associated with the multistep DRIE process, giving results slightly better than expected for metal-machined waveguides. This process enables the integration of multiple terahertz waveguide components such as mixers, multipliers, quadrature hybrids, and polarization twists onto a single silicon package.

High‐accuracy silicon‐on‐insulator accelerometer with an increased yield rate

This Letter presents a high accuracy silicon-on-insulator (SOI) capacitive accelerometer using a backside dry release process. To increase the yield rate of the process, the deep reactive iron etching (DRIE) process was improved using a grooved accompany wafer to balance the pressure inside the back cavity of the SOI devices. By using this method, almost all the devices after the DRIE will not crack. Thus, the yield rate is significantly increased. Furthermore, the DRIE process was improved by dividing the DRIE process into four stages to decrease the tilt angle of DRIE. It is experimentally demonstrated that the tilt angle of the side wall was decreased from 0.81° to 0.27° and the loss of the capacitive sensitivity caused by the error was decreased from 28 to 8%. Test results show that sensitivity, bias stability, and noise floor of the accelerometer is 3.1 V/g, 16 μg, and 3.1 μg/√Hz, respectively.

Study of High Aspect Ratio NLD Plasma Etching and Postprocessing of Fused Silica and Borosilicate Glass

In this paper, we report magnetic neutral loop discharge (NLD) plasma etching of fused silica (FS) and borosilicate glass (BSG), demonstrating high aspect ratio deep etch (100 μm) with vertical walls (<;3° deviation from vertical). This paper for the first time presents the systematic study of FS and BSG deep etching in NLD plasma. Four different masking materials have been explored including metal, amorphous silicon, bonded silicon, and photoresist. Etch parameters were optimized to eliminate unwanted artifacts, such as micro-masking, trenching, and faceting, while retaining a high aspect ratio (up to 7:1 for FS and 8:1 for BSG). In addition, a method for sidewall roughness mitigation based on postfabrication annealing was developed, showing the sidewall roughness reduction from the average roughness (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ) 900 to 85 nm. Further advances in deep plasma etching processes may enable the use of FS and BSG in the fabrication of precision inertial MEMS, micro-fluidic, and micro-optical devices.

Plasma chemical etching of high-aspect-ratio silicon micro- and nanostructures

High-aspect-ratio (HAR) silicon etching of micro-and nanostructures in a time-multiplexed deep etching process (Bosch process) is reviewed, including applications, different technological methods, critical challenges, and main principles of the technologies. HAR silicon etching is an application associated primarily with micro- and nanostructures. This potentially large-scale application requires HAR etching with a high throughput and controllable profile and surface properties. The most significant effects like RIE lag, bowing, stop effect, and profile shape dependence are discussed.

Extreme hydrophobicity and omniphilicity of high-aspect-ratio silicon structures

We present an application of high-aspect-ratio (high-AR) silicon structures (black silicon) with high water repellency and good wettability by oils and solvents. The fabrication of black silicon consists of a deep reactive-ion etching process for extremely-high-AR silicon structures and surface treatment with C 4 F 8 gas. Such high-AR structures were found to be highly resistant against wetting by water, but they also have good wetting characteristics with respect to certain liquids such as ethanol, hexane and mineral oil. To determine the relationship between the AR of nanostructures and wetting selectivity, four different black silicon samples with different pattern heights were used. The static contact angles of various liquid were measured for the analysis of wetting properties of the four black silicon samples. To explore feasible applications, ethanol–water separation was performed as a miniaturized experimental simulation of environmental remediation.

Silicon-Based White LED Packaging Module With an Integrated RGB Color Sensor

This letter presents a silicon-based light-emitting diode (LED) packaging module with integrated red, green, and blue (RGB) color sensors, which can detect the variations in the brightness and specified wavelength intensity of white LEDs to evaluate the chromaticity and color temperature of emitting light in real time. The carrier substrate with color sensors was fabricated by semiconductor manufacturing technology and a deep silicon etching process was used to complete electrical division and thermal isolation. By integrating blue LED and silicone phosphor, a monolithic packaging module with miniaturization and low cost was achieved. A typical experimental result shows the output currents of the RGB color sensors as 0.082, 0.086, and 0.068 mA, respectively, when the input current to the LED is 0.2 A. The calculated chromaticity coordinates of x and y are 0.35 and 0.36, respectively, and the corresponding color temperature is 4852 K. These experimental results are consistent with the measurements of a commercial luminous meter.

Highly uniform sieving structure by corner lithography and silicon wet etching

We describe and demonstrate a fabrication process for silicon sieves with highly-uniform, micron-sized pyramidal shaped pores featuring squared apertures. These sieves are fabricated over areas of several square millimetres by means of double-side standard UV-lithography and wet etching in (100)-silicon. We intend to use these sieves for hydrodynamic cell capture devices (sieves), suitable for integration of electrodes for electrophysiological measurements of neuronal networks. For the fabrication process, standard plain silicon wafers are used, without the need for etch-stop layers or silicon-on-insulator. To ensure that the sieve contains pores with identical aperture sizes by merely the use of a timed etch-stop, sacrificial octahedral structures are formed underneath each pore by means of corner lithography. These sacrificial structures counteract non-uniformities in the thickness of the layer defining the sieve, resulting from the deep (>500μm) anisotropic backside wet etch process. For our intended use, we aimed for pyramidal pits with a base length of 20μm and an aperture at their tips of 3μm over a circular sieve area with a diameter of 2.4mm. In order to minimize the non-uniformity in sieve thickness, the deep back-etch is studied by applying KOH and TMAH etchants using variations in temperature of the etchant as well as variations in size and shape of the applied mask opening on the backside of the silicon substrate. With optimal conditions, both etchants can be used to successfully realize sieves. However, the best results are obtained for a back-etch in TMAH (25wt%, 71°C) with Triton X (0.1vol%) as an additive. The later conditions yield a non-uniformity of 0.7μm for a sieve thickness of 18μm. Within the sieve area, all 900 square pores, evenly distributed with a 70μm pitch, have an aperture of 3.2±0.1μm.

Three-dimensional simulation of surface topography evolution in the Bosch process by a level set method

A deep reactive ion etching (DRIE) process (Bosch process) is used extensively in the fabrication of microelectromechanical systems (MEMS). Modeling and simulation studies have helped improve our understanding and process design. The Bosch process consists of multiple cycles of alternating etching and deposition steps. Based on a narrow band level set method, by integrating etching simulation and deposition simulation modules, a simulation system is proposed for three-dimensional (3-D) simulation of the Bosch process with arbitrarily complex mask shapes. To verify the simulation system, a series of simulations and experiments have been performed. The simulation results are in good agreement with the experiments. The method may be used to optimize the practical Bosch process and to design and control the profile of high-aspect ratio microstructures.

Process Parameters Effect on Deep Silicon Etching for High Density Capacitor Structure

In deep silicon etching process, there have been many investigations on etching rate. However, only few published papers mentioned the sidewall roughness, which is a critical issue for NMES/MEMS application. In this work, we encountered a special phenomenon: sidewall damage, which was firstly observed during deep silicon etching. Various process parameters such as chamber pressure, bias power, passivation gas flow and etch time have been investigated using a conventional two steps Bosch process for high density Metal-insulator-metal (MIM) capacitor application. During the etching, obvious sidewall damage can be observed in the etched trench sidewall. It can be noted its starting depth has a close dependence on process parameters such as chamber pressure and bias power, which play a significant role influencing etching profile and trench depth. At a lower pressure, a smooth sidewall without any damage can be achieved. With pressure increasing above a certain value, sidewall damage has almost occurred in the full trench, which will lead a series of severe issues such as poor conformal deposition of high-k insulation film, discontinuity of the electrode layer, and reliability failures in MIM capacitor structure.On the other hand, at a given pressure, bias power has a direct effect on etching profile and sidewall damage. As bias power increases, etching profile becomes more negative from vertical one. In particular, sidewall damage is not located in certain depth range but distributed in almost whole trench sidewall and, multi-bowing profile can be seen with increasing etching depth.According to the experimental results, an etching mechanism has been presented to explain the etching phenomena by the ion angular distribution function (IADF) fundamental. Finally, by optimizing process parameters, a perfectly smooth profile without any sidewall damage can be obtained having an aspect ratio as high as 30 with 5μm width.

Smooth silicon sidewall etching for waveguide structures using a modified Bosch process

We present a method to etch vertical and smooth silicon sidewalls. The so-called modified Bosch process combines a passivation step, a breakthrough step, and an anisotropic etch step within one repeatable loop. Thanks to the sidewall protection from the passivation step and the anisotropic nature of the etch step, this method can etch smoother silicon sidewalls than either a typical Bosch process or a continuous anisotropic etch process. The silicon sidewall of a 4-μm-deep waveguide structure etched by this method has a root mean square roughness below 10 nm and a peak-to-valley (P-V) roughness below 60 nm. Comparisons between silicon waveguides etched by this process and by another deep reactive-ion etching process showed remarkable improvement in propagation loss at the wavelength of 1550 nm.

Разработка процесса глубокого плазменного травления кремния для технологии трехмерной интеграции кристаллов

Plasma etch process for thought-silicon via (TSV) formation is one of the most important technological operations in the field of metal connections creation between stacked circuits in 3D assemble technology. TSV formation strongly depends on parameters such as Si-wafer thickness, aspect ratio, type of metallization material, etc. The authors investigate deep silicon plasma etch process for formation of TSV with controllable profile. The influence of process parameters on plasma etch rate, silicon etch selectivity to photoresist and the structure profile are researched in this paper. Technology with etch and passivation steps alternation was used as a method of deep silicon plasma etching. Experimental tool «Platrane-100» with high-density plasma reactor based on high-frequency ion source with transformer coupled plasma was used for deep silicon plasma etching. As actuation gases for deep silicon etching were chosen the following gases: SF6 was used for the etch stage and CHF3 was applied on the polymerization stage. As a result of research, the deep plasma etch process has been developed with the following parameters: silicon etch rate 6 µm/min, selectivity to photoresist 60 and structure profile 90±2°. This process provides formation of TSV 370 µm deep and about 120 µm in diameter.

High sensitive/wide dynamic range, field emission pressure sensor based on fully embedded CNTs

The formation of high sensitivity–wide dynamic range field emission pressure sensors based on carbon nanotubes (CNTs) is reported. In this work, CNTs are grown inside an array of micromachined holes in order to ensure a high sensitivity and a wide dynamic range by allowing anode–cathode proximity while preventing anode–cathode direct contact simultaneously. External pressure is applied to a Si-based flexible anode, which results in consequent variations in emission current, due to electric field changes. Microcavities in this structure have been formed by a Si deep vertical etching process, while the CNTs have been grown by direct current plasma-enhanced chemical vapour deposition. Also, it is demonstrated that a similar fabrication process can be applied to implement a device with an electrically controllable emission current. A high sensitivity of 1.5–13.7 µA kPa−1 (with Vanode/cathode < 100 V) within a dynamic range from around 0.1 to 1 GPa, is measured in this experiment.

A study on the deep etching and ohmic contact process of 6H-SiC high-temperature pressure sensor

In all the process steps of manufacturing high-temperature pressure silicon carbide sensors, deep etching and ohmic contact are two crucial processes. Reactive ion etching is used for the deep etching of silicon carbide in our experiment, and the surface has a high quality after etching. Using nickel as the mask material on the C layer by electroplating, the depth of deep etching reaches about 81 µm and the thickness uniformity is fairly good, fluctuating within 200 nm or less. The Ti–TiN–Pt system is proposed for metallization, in which Ti, TiN and Pt are used as the contact layer, the diffusion impervious layer and the lead interaction layer, respectively. The Kelvin test shows that stable ohmic contact is achieved and a specific contact resistivity of 8.42 × 10−4Ω cm2 is detected. The etching depth of 81 µm meets the requirement of forming a sensitive circular membrane, and the metal system of Ti–TiN–Pt ensures reliable connection and stable ohmic contact between the metal and semiconductor at high temperatures.

Amorphous fluoropolymer protective coatings for front-side MEMS releasing by hydrofluoric acid vapor etching

Vapor-phase hydrofluoric acid (HF) sacrificial layer etching is frequently used in the microelectromechanical systems (MEMS) industry because it allows freestanding microstructures to be released without sticking to the substrate and does not require time-consuming and expensive deep reactive-ion etching (DRIE) processes. However, due to process complexity and limited protectable duration in previous work, an effective surface protecting method by using easily coated and removed films is still under development.In this work, we present a novel approach of spinning an amorphous fluoropolymer coating to protect the microstructures of the passivation layer and metal electrodes from HF vapor attack. The HF-resistant capability of the amorphous fluoropolymer is assessed, and the results demonstrate that the proposed method has advantages of lower cost and easier processing compared with the complicated process used for fabricating inorganic films. Through the use of a post-bake temperature lower than 220°C within a single additional process that lasts for less than 2h, an amorphous fluoropolymer coating can be treated and coated in a protective layer thinner than 4μm that can withstand an HF vapor etching application period of longer than 30min. Using this method, we successfully fabricated a target MEMS device with front-side release by HF vapor etching in which the remaining microstructures were well protected.

MEMS-Based Gas Chromatography Column for the Analysis of Chemical Warfare Agent (CWA) Simulates

In this report the gas chromatography column was fabricated base on micro electro mechanical system (MEMS) technology. It tries to find an equilibrium point which can fast detect CWA stimulants with efficient column separation. Under deep reactive-ion etching (DRIE) process, a 1m length, 90 um thickness and 300 um height which form 3:1high-aspect-ratio, MEMS-based silicon GC column was fabricated. The GC column was coated with 95%Methyl 5% Phenyl Polysilozane (DB-5) as the stationary phase. Dimethyl methyl phosphonate (DMMP), Triethyl phosphate (TEP) and Methy salicylate were used for CWA simulations. All of these three samples can be separated less than 90s with reasonable column efficiency.

Potassium hydroxide polishing of nanoscale deep reactive-ion etched ultrahigh aspect ratio gratings

A fabrication process has been developed to chemically polish the sidewalls of 200 nm-pitch gratings via potassium hydroxide (KOH) etching following the Bosch deep reactive-ion etching (DRIE) process. Previous KOH polishing experiments focused on micron scale features. This work is the first reported combined DRIE-KOH etching process on the nanoscale for ultrahigh aspect ratio structures with feature sizes 30 times smaller than previously published work. The primary application of the gratings is x-ray spectroscopy and requires polished sidewalls for efficient x-ray reflection. Polishing is also critical for increasing the open area by narrowing the grating bars, which increases the throughput of x-rays. The increased open area is also valuable for other applications such as ultraviolet filtration, neutron spectroscopy and biofiltration. Advanced Bosch processes leave approximately 4 nm, root mean square (RMS), of roughness on the sidewalls. This roughness needs to be reduced to below 1 nm to efficiently reflect soft x-rays with wavelengths between 1 and 5 nm. Furthermore, high aspect ratio DRIE can result in bar width variations of approximately a factor of two from the top to the middle of the channel, commonly referred to as bowing. The polishing procedure presented here removes the roughness to below the resolution of the scanning electron microscope, and was measured via an atomic force microscope to be less than 1 nm RMS. The bowing has also been reduced by at least a factor of 3. The polishing process takes advantage of the anisotropy of KOH silicon etching. Specifically, the {111} silicon planes etch approximately 100 times slower than other crystal planes. This anisotropy allows the grating bars to be etched in 50% by weight KOH at room temperature for up to 60 min. Long etches have several key requirements, including 0.2 degree alignment of the grating with respect to the {111} planes, mask roughness below 40 nm and minimal defects in the silicon. If these requirements are not met, the grating will quickly be destroyed by the etch, which etches the non-{111} planes in excess of 1 μm per hour. The fabrication steps of this work are described in detail including a novel technique to align the 200 nm-pitch interference lithography image grating to the {111} planes of a ⟨110⟩ silicon wafer.

Silicon Micromachined Lens Antenna for THz Integrated Heterodyne Arrays

In this paper, we present the design, fabrication, and measurements of a lens THz antenna that can be fabricated using conventional photolithography and deep reactive etching processes. The antenna is composed of an extended hemispherical silicon lens and a leaky wave waveguide feed. Both elements are fabricated using silicon micromachining techniques, enabling the fabrication of future large antenna arrays with a parallel process. To show the concept, a first antenna prototype has been fabricated using this fabrication process. Measurements obtained at 550 GHz are presented.

Controllable fabrication of periodic arrays of high-aspect-ratio micro-nano hierarchical structures and their superhydrophobicity

This paper demonstrates a flexible and controllable fabrication of vertically aligned and high-aspect-ratio (HAR) micro-nano hierarchical structures using conventional micro-technologies. We first masked the nanopatterns on a photoresist mold by shifting the same photomask, which could be performed using conventional contact microlithography. Thereby replicating nanopatterns onto an aluminium mold and successfully fabricating silicon nanopillar arrays about 300 nm in diameter and 5 µm in height via the deep reactive etching (DRIE) process. We also fabricated micro-nano hierarchical structures with variable aspect ratios using the proposed nanopattern technology and DRIE process without using any special nanopatterning equipment or techniques. The proposed method not only simplified the fabrication process but also produced HAR (higher than 15) structures. We also investigate the replica molding steps from the fabricated silicon stamp to a UV-curable polymer replica using a PDMS mold and conventional nano-imprinting, where each nanopillar diameter was 320 nm with 95% fidelity. As a result, the hierarchical structure arrays show stable superhydrophobic surface properties with a contact angle of approximately 160°. Owing to the cost efficiency of mass production and the fidelity of the strategy, the methodology could provide a general approach for fabricating complex three-dimensional periodic hierarchical structures onto a single chip and can be applied to various fields of multifunctional applications.

A SOI-MEMS Piezoresistive Atmosphere Pressure Sensor

In this paper, a SOI-MEMS (silicon on insulator- micro electro mechanical system) pizeoresistive atmosphere pressure sensor is presented using anodic bonding. Differently from the prevailing fabrication process of silicon piezoresistive pressure sensor: the device layer monocrystalline of SOI silicon wafer is used as the strain gauge with a simple deep etching process; and the SiO2 layer of SOI silicon wafer as the insulator between strain gauge and substrate. The whole fabrication processes of the designed sensor are very simple, and can reduce the cost of sensor. The Pressure-Voltage characteristic test results suggest a precision within 0.14% in linear fitting. It is shown that the temperature coefficient is 2718ppm/°C from the Typical temperature curve of the pressure sensors.