Dedicated Hardware Units Research Articles

Comparison of Modern Omnidirectional Precise Shadowing Techniques Versus Ray Tracing

AbstractThis paper presents an in depth comparison of state‐of‐the‐art precise shadowing techniques for an omnidirectional point light. We chose several types of modern shadowing algorithms, starting from stencil shadow volumes, methods using traversal of acceleration structures to hardware‐accelerated ray‐traced shadows. Some methods were further improved – robustness, increased performance; we also provide the first multi‐platform implementations of some of the tested algorithms. All the methods are evaluated on several test scenes in different resolutions and on two hardware platforms – with and without dedicated hardware units for ray tracing. We conclude our findings based on speed and memory consumption. Ray‐tracing is the fastest and one of the easiest methods to implement with small memory footprint. The Omnidirectional Frustum‐Traced Shadows method has a predictable memory footprint and is the second fastest algorithm tested. Our stencil shadow volumes are faster than some newer algorithms. Per‐Triangle Shadow Volumes and Clustered Per‐Triangle Shadow Volumes are difficult to implement and require the most memory; the latter method scales well with the scene complexity and resolution. Deep Partitioned Shadow Volumes does not excel in any of the measured parameters and is suitable for smaller scenes. The source codes of the testing framework have been made publicly available.

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

High throughput token driven FSM based regex pattern matching for network intrusion detection system

A single core SRAM memory with a unified memory controller is proposed for regex patterns which contains complex signatures. Many existing NIDS systems are based on token stream with dedicated hardware units to accommodate byte oriented matching with moderate network throughput rate. The overall NIDS performance metrics is degraded when the number of bytes in the database increased. It will lead the demands of coordinated payload monitoring scheme in any memory based digital NIDS system. In this work, a bit based pattern matching algorithm with FSM state transition is proposed which gives both parallel processing and network assertion payload validity check during the conversion of segments into tokens. The Finite State Machine state controller is used in early misdetection to optimize overall matching time in case of segments with multiple non-trivial tokens where the regex patterns are divided into sub-patterns and the concurrent matches are halted in a parallel manner. Finally synchronization problem during hierarchical state transition and vector matching over multiple pages unique SRAM controllers are used which is driven with fully down converted sub-groups. The efficiency of proposed NIDS system over moderate intrusion database process is proved in terms of classification rate. Hence, proposed NIDS system consumes lesser memory resources and it is verified through comparison with state-of-the-art methods.

Embedded registration of visible and infrared images in real time for noninvasive skin cancer screening

We present an embedded system architecture that implements real-time multimodal registration to enable dual-camera spatio-temporal feature extraction in a skin cancer screening application. We test the system on a combination of visible and long-wave infrared image sequences, but it can be easily extended to setups operating in different sections of the spectrum. Image registration is performed by matching common features between each frame of a visible image to each frame of an infrared image sequence to estimate a projective transformation between them. The parameters of this transformation are estimated recursively on line with the video, thus enabling image registration in real time. The algorithm is implemented using a combination of embedded software and dedicated hardware units on a heterogeneous reconfigurable system-on-a-chip. The hardware performs feature detection and extraction, while the software estimates the transformation parameters and maps each visible video frame onto the infrared image coordinates. Implemented on an FPGA, our prototype runs at 540 frames per second with a 135 MHz clock, consumes 1.8 W and utilizes 29% and 54% of the logic and multiplier resources of the chip, respectively.

MEMORY-Based Hardware Architectures to Detect ClamAV Virus Signatures with Restricted Regular Expression Features

We aim to implement a single-chip hardware detection engine for virus scanning. Our study is based on the ClamAV virus database, which contains 88.9K strings and 9.6K extended hex-signatures with restricted regular expression (regex) features. We have previously presented cost-effective hardware architectures to detect the 88.9K strings and 3.2K regex patterns that are composed of multiple string segments. In this paper, we shall present hardware architectures to detect the remaining 6.4K regex patterns. Our method is based on the information reduction approach. We transform the byte-oriented matching problem to a token-based matching problem. A regex pattern contains one or more segments, and a segment may be subdivided into multiple non-trivial tokens. In general, a token is associated with one or a few regexes only. The input byte-stream is converted into a token-stream using dedicated hardware units, where the number of tokens is much less than the number of bytes. The token-stream is processed by a NFA-based aggregation unit to determine if any segment can be found. Detected segments are further processed by a scoreboard to determine if any multi-segment pattern can be found. For proof-of-concept, our method is implemented on a Virtex-6 FPGA which consumes 1.84 MB on-chip memory.

Channel Efficiency with Security Enhancement for Remote Condition Monitoring of Multi Machine System Using Hybrid Huffman Coding

This paper presents a novel scheme of remote condition monitoring of multi machine system where a secured and coded data of induction machine with different parameters is communicated between a state-of-the-art dedicated hardware Units (DHU) installed at the machine terminal and a centralized PC based machine data management (MDM) software. The DHUs are built for acquisition of different parameters from the respective machines, and hence are placed at their nearby panels in order to acquire different parameters cost effectively during their running condition. The MDM software collects these data through a communication channel where all the DHUs are networked using RS485 protocol. Before transmitting, the parameter’s related data is modified with the adoption of differential pulse coded modulation (DPCM) and Huffman coding technique. It is further encrypted with a private key where different keys are used for different DHUs. In this way a data security scheme is adopted during its passage through the communication channel in order to avoid any third party attack into the channel. The hybrid mode of DPCM and Huffman coding is chosen to reduce the data packet length. A MATLAB based simulation and its practical implementation using DHUs at three machine terminals (one healthy three phase, one healthy single phase and one faulty three phase machine) proves its efficacy and usefulness for condition based maintenance of multi machine system. The data at the central control room are decrypted and decoded using MDM software. In this work it is observed that Chanel efficiency with respect to different parameter measurements has been increased very much.

A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems

Spatial division multiplexing (SDM) in MIMO technology significantly increases the spectral efficiency, and hence capacity, of a wireless communication system: it is a core component of the next generation wireless systems, e.g. WiMAX, 3GPP LTE and other OFDM-based communication schemes. Moreover, spatial division multiple access (SDMA) is one of the widely used techniques for sharing the wireless medium between different mobile devices. Sphere detection is a prominent method of simplifying the detection complexity in both SDM and SDMA systems while maintaining BER performance comparable with the optimum maximum-likelihood (ML) detection. On the other hand, with different standards supporting different system parameters, it is crucial for both base station and handset devices to be configurable and seamlessly switch between different modes without the need for separate dedicated hardware units. This challenge emphasizes the need for SDR designs that target the handset devices. In this paper, we propose the architecture and FPGA realization of a configurable sort-free sphere detector, Flex-Sphere, that supports 4, 16, 64-QAM modulations as well as a combination of 2, 3 and 4 antenna/user configuration for handsets. The detector provides a data rate of up to 857.1 Mbps that fits well within the requirements of any of the next generation wireless standards. The algorithmic optimizations employed to produce an FPGA friendly realization are discussed.

New approach to develop a system solution for an integrated multi-service system

This paper presents a system solution for an integrated multi-service system (IMSS) in the field of digital TV (DTV). Key element of this system is a motion picture media processor which is based on an integrated RISC CPU, scalable DSP modules and dedicated hardware units. This concept is targeted not only for the pure reception of digital TV, but also for the interactive processing of broadcasted data. High computational performance and scalability realize the enabling functionality for new media applications.

Hardware support for distributed real-time operating systems

This paper presents a hardware architecture for supporting distributed real-time operating systems. It proposes the use of dedicated hardware units for running task scheduling and communication, in order to alleviate the load on the precursor responsible for running the application tasks. These hardware units also compute the execution time of applications tasks, and other statistics that can be taken into account by more sophisticated scheduling algorithms. The proposal enhances the overall system predictability. Since it is based on low-cost microcontrollers, it represents a cost-effective alternative for developing low-cost distributed real-time systems.

Hardware Support for Distributed Real-Time Operating Systems

This paper presents a hardware architecture for supporting distributed realtime operating systems. It proposes the use of dedicated hardware units for running task scheduling and communication, in order to alleviate the load of the processor responsible for running the application tasks. These hardware units also compute the execution time of application tasks and other statistics that can be taken into account by more elaborated scheduling algorithms. The proposal enhances the overall system predictability. Since the proposal is based on low-cost microcontrollers, it represents a cost-effective proposal for developing low-cost distributed real-time systems.