Decoupled Plasma Nitridation Research Articles

Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

Q-factor is a reasonable index to investigate the integrity of circuits or devices in terms of their energy or charge storage capabilities. We use this figure of merit to explore the deposition quality of nano-node high-k gate dielectrics by decoupled-plasma nitridation at different temperatures with a fixed nitrogen concentration. This is very important in radio-frequency applications. From the point of view of the Q-factor, the device treated at a higher annealing temperature clearly demonstrates a better Q-factor value. Another interesting observation is the appearance of two troughs in the Q-VGS characteristics, which are strongly related to either the series parasitic capacitance, the tunneling effect, or both.

Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments

Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of high-dielectric-constant (high-K) materials to promote drive current in deep nano-node devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values.

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

In order to improve the low-frequency noise of input/output (I/O) p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a 5 nm SiO2/2 nm HfO2/5 nm TiN gate stack for DRAM applications, different post-deposition treatments have been investigated. Decoupled Plasma Nitridation with various strengths is compared with an SF6 plasma anneal. Wafers with and without an Al2O3 cap, serving as a threshold voltage shifter have also been included in the study. It is shown that the best results, i.e. the lowest 1/f noise magnitude, have been found for the SF6-treated I/O pMOSFETs, reaching in the best case a value comparable with SiO2/polycrystalline silicon reference devices.

Electrical stress probing recovery efficiency of 28 nm HK/MG nMOSFETs using decoupled plasma nitridation treatment

Exposing the feasible nitrogen concentration and annealing temperatures with decoupled plasma nitridation (DPN) treatment to the high-k dielectric after deposition as gate dielectric is impressive to raise the high-k value and against the gate leakage. The study not only focuses on the quality of high-k dielectric, but the reliability concern. Using the voltage stress sensing and analyzing the recovery of gate dielectric, comparing with different nitrogen concentration and different annealing temperatures is done. The consequences show the tested device with higher annealing temperature has the better performance rather than the lower one in recovery and drive current, but the worse in reliability stress, especially in threshold voltage (VT) shift. If the tested devices were under the same nitridation treatment, the performance and recovery efficiency of the tested device with the lower nitrogen concentration are better than those of the higher one, but the degradation rate is more distinct.

Treatments for reliability improvement in thick oxides diffusion and gate replacement I/O transistors

In this work, the negative bias temperature instability (NBTI) performance for HKMG and diffusion and gate replacement (D&GR) input/output (I/O) devices is investigated. Even though NBTI performances of D&GR transistors are aligned with conventional HKMG (high-k/metal gate) integration with thin oxide devices, it is not the case for thick oxide I/O devices. In particular, it is shown that strong lifetime degradation is observed as soon as high-k layers are deposited on top of the thick interfacial layer. The NBTI degradation is correlated to a diffusion of Ti/Hf (potentially Al) elements from the HKMG gate stack down to the interfacial layer. Directions for reliability improvement treatments are then defined. It is shown that decoupled plasma nitridation (DPN) and fluorine implant could greatly improve NBTI performance, through an improvement of interface and bulk (inside SiO2 interfacial layer) defect density. Device trade-offs are also investigated for the DPN treatments and fluorine implants cases.

Influence of I/O oxide process on the NBTI performance of 28 nm HfO2-based HKMG p-MOSFETs

The NBTI (negative bias temperature instability) performance of 28nm HfO2-based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

Influence of ISSG tunnel oxide with decoupled plasma nitridation on erase characteristic of NOR-type floating-gate flash memories

This paper investigated the influence of ISSG (in situ steam generation) tunnel oxide layer with decoupled plasma nitridation (DPN) on the erase reliability of NOR-type floating-gate flash memory devices. The experimental results demonstrated that the tunnel oxide with ISSG process achieves better thickness uniformity and higher breakdown voltage than that with conventional dry oxidation process. However, the erase performance of flash cells was significantly degraded when DPN was applied to the ISSG oxide. The higher bulk nitrogen content from DPN process could lead to more bulk traps generation by substituting the strong Si–O bonds for the weak Si–N bonds in the tunnel oxide. During program/erase cycling, the more electrons trapped in the bulk tunnel oxide the less the FN erase electric field will be, which is responsible for the degradation of erase performance.

Comparison of electrical characteristics for SiONx and HfZrOx gate dielectrics of MOSFETs with decoupled plasma nitridation treatment

Display Omitted The gate leakage with oxynitride dielectric around 1.5nm thickness was sensed.The gate leakage with HfZrOx dielectric around 1.5nm thickness was extracted.The ON currents for both d...

Comparison of electrical characteristics for SiONx and HfZrOx gate dielectrics of MOSFETs with decoupled plasma nitridation treatment

The gate leakage with oxynitride (SiONx) as a gate dielectric is lower than that with high-K (HfZrOx) around one order at VGS=±0.8V under the close physical gate thickness (∼1.5nm) and device geometry. The subthreshold swing value in n-channel device grown with SiONx plus poly-Si gate is also superior to that for high-K gate dielectric with metal gate, but the phenomenon in p-channel device is changed due to the boron penetration from gate to channel surface. On the basis of the extracted data, the entire ON current with high-K dielectric is still better than that with oxynitride. The raise-up ratio is up to the maximum 51%. Although the possible existence of nano-crystallization, trap species or oxygen vacancy in high-K is increased to indirectly advance the higher leakage, the desired benefit to promote the drive current is still approached.

Kink effect for 28 nm n-channel field-effect transistors after decoupled plasma nitridation treatment with annealing temperatures

The kink effect of drain leakage based on gated diode measurement metrology for the tested nMOSFETs with 28 nm HK/MG, gate–last and PDA or DPN nitridation processes was observed at VG around −0.6 V when the gate voltage was swept from −Vcc to 0.2 volt as VD = 0.1 V. Nevertheless, this interesting phenomenon was not evident as the gate voltage was reversely swept from 0.2 volt to -Vcc. The chief mechanism in speculation can be illustrated by the electrons coming from drain inducing capture–and–emission behaviour by the channel interface traps near the drain junction. While VG changes from −Vcc towards +0.2 V, interface states near valence band become lower than Fermi–level of silicon substrate. Electrons flow from drain to fill these interface states so that drive current (ID) increases. On the contrary, as VG changes from +0.2 V to −Vcc, the trapped electrons are recombined with holes from substrate so that ID is not affected. This kink effect for all of tested devices is not very distinct far and near. When the Poole–Frenkel (P–F) tunnelling electrons coming from gate to drain are evident in leakage, especially at the long–channel device, this effect will be probably counteracted, exhibited at the electrical characteristics of PDA group.

Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment

A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gate-last integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.

Modification of Early Effect for 28-nm nMOSFETs Deposited With HfZrO<sub><italic>x</italic></sub> Dielectric After DPN Process Accompanying Nitrogen Concentrations

The model of the Early effect at nanonode devices should be modified owing to the unignored contribution of vertical gate field. This effect is more obvious when the channel length is decreased more. Using higher decoupled plasma nitridation nitrogen treatment after high-k dielectric deposition, besides enhancing the drive current due to promoting the microscopic homogeneity of the Hf-based film, seems also to little suppress the Early effect. This phenomenon at L = 0.03 μm device is proved and due to the lower β-slope of influencing the high-vertical field.

0.13㎛ 기술의 shrink에 따른 DC Parameter 매칭에 관한 연구

본 논문은 기존의 poly length만의 축소와 달리 입, 출력 소자를 포함한 core 디바이스의 <TEX>$0.13{\mu}m$</TEX> 디자인을 10% 축소하는 것으로 여러 채널 길이에 따른 body effect와 doping profile simulation을 해석하였다. 축소 전의 DC 파라미터 매칭을 위하여 게이트 산화막의 decoupled plasma nitridation 처리와 LDD(Lightly Doped Drain) 이온주입 전 TEOS(Tetraethylortho silicate) 산화막 <TEX>$100{\AA}$</TEX> 그리고 LDD 이온주입을 22o tilt-angle(45o twist-angle)로 최적화하였고 그 결과 축소 전의 5%의 범위에서 매칭됨을 확인하였다. This paper relates 10% shrink from <TEX>$0.13{\mu}m$</TEX> design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide <TEX>$100{\AA}$</TEX> before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

Decoupled Plasma Nitridation에 의한 Flicker 노이즈 개선에 관한 연구

본 논문은 <TEX>$0.13{\mu}m$</TEX> 기술의 디자인을 10% 축소하는데 기존의 로직 디바이스만의 축소와는 달리 로직뿐 아니라 입, 출력 회로의 축소에 관한 것이다. 게이트 산화막(1.2V)을 decoupled plasma nitridation(DPN) oxide로 변경함으로써 flicker 노이즈를 축소 전 공정에 비해 1/3-1/5배 감소됨을 확인하였다. 또한, 축소에 의한 피할 수 없는 문제는 일반적인 metal insulator metal(MIM)의 캐패시터 문제이다. 이를 해결하기 위하여 20% 높은 MIM 캐패시터(<TEX>$1.2fF/{\mu}m^2$</TEX>)를 개선하고 그 특성을 평가하였다. This paper relates 10% shrink from <TEX>$0.13{\mu}m$</TEX> design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor (<TEX>$1.2fF/{\mu}m^2$</TEX>) was developed and its performance were evaluated.

Threshold Voltage Adjustment for 28nm HfO&lt;sub&gt;x&lt;/sub&gt;/ZrO&lt;sub&gt;x&lt;/sub&gt;/HfO&lt;sub&gt;x&lt;/sub&gt; Gate Dielectric of nMOSFETs Using DPN Process with Annealing Temperatures

Following the investigation of the relationship among the annealing temperatures for decoupled plasma nitridation (DPN) process to indirectly manipulate the amount of oxygen vacancy in high-k (HK) gate dielectric, the expected threshold voltage (Vt) of n-channel MOSFET (nMOSFET) device is able to be approached. The uniformity of Vt values related to the channel lengths was fine due to 10% deviation specification, but the roll-up phenomenon coming from the strain effect was observed. The lower annealing temperature shows the higher Vt value due to the higher interface state density, reflecting at the subthreshold swing (S.S.) characteristics.

Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation

Germanium Oxynitride (GeON) gate interlayer (IL) dielectric formed using decoupled plasma nitridation (DPN) technique is compared with GeO2 and thermally nitrided GeON ILs for Ge gate stack applications using n-channel capacitors and transistors. Lower nitrogen concentration and roughness at the GeON/Ge interface lead to lower midgap interface trap density (Dit) and 1.5× higher electron mobility for the DPN versus thermally nitrided GeON IL. DPN GeON IL also exhibits enhanced thermal stability till 575 °C at the expense of a small degradation in Dit versus GeO2 IL, making it a more viable gate IL dielectric on Ge channels.

Dependence of the relative sensitivity factor of nitrogen on various oxynitride dielectric matrixes

The relative sensitivity factor (RSF) plays a critical role in the quantification of nitrogen concentration in oxynitride gate oxide measured using secondary ion mass spectrometry (SIMS). The RSF depends primarily on the matrixes where the nitrogen resides under conditions in which the parametric settings of the SIMS equipment remain unchanged. In this article, different types of oxynitride dielectric films have been prepared under several different fabrication processes including decoupled plasma nitridation, thermal nitridation by nitric oxide (NO) and nitrous oxide (N2O), which resulted in the formation of significantly different chemical bonding and micro-structures for the oxynitride. The nitrogen RSF values of these oxynitride films were determined using the ratio of the species SiN− and 30Si− from the Time-of-Flight SIMS. It was found that the overall RSF values from the point-by-point algorithm ranged from 1.15×1021 to 2.41×1021 atoms/cm3. These account for about 2 times the difference in the RSF values.

Improved Nitridation of GeO2 Interfacial layer for Ge Gate Stack Technology

ABSTRACTNitridation of GeO2 interfacial layer (IL) was done using continuous wave (CW) and pulsed wave (PW) decoupled plasma nitridation (DPN) processes. Langmuir probe analysis of the N2 plasma demonstrates that at the same effective power and pressure, PW plasma has similar electron density (Ne) with lower electron temperature (kTe) and plasma potential (Vp) as compared to CW plasma. This results in softer plasma conditions using a PW process leading to lower plasma-related damage in the IL, but without reducing the overall nitrogen concentration. The plasma parameters were further correlated to mobility (μ) and interface trap density (Dit) extracted from fabricated Ge n-MOSFETs. As expected from the plasma analysis, at the same effective power and pressure, the PW DPN process shows 1.2X higher electron mobility as compared to a CW process. This improvement can enable GeON as an IL for future Ge CMOS gate stack technology.

Comparison of equivalent oxide thickness and electrical properties of atomic layer deposited hafnium zirconate dielectrics with thermal or decoupled plasma nitridation process

The NH3 thermal annealing and decoupled plasma nitridation (DPN) processes are compared for the equivalent oxide thickness (EOT) scaling of atomic-layer-deposited hafnium zirconate (HfZrO2) gate dielectric. Detailed physical, optical, and electrical characteristics of nitrided HfZrO2 (HfZrON) film are reported. It is found that DPN can yield a thinner SiOx interfacial layer (IL) (about 0.12 nm more in terms of EOT scaling) and a more densified HfZrO2 layer compared to those obtained using NH3 thermal annealing at a 16% nitrogen dose. NH3 thermal nitridation causes a large nitrogen distribution tail at the SiOx IL/Si substrate interface and increases leakage current, which suppresses EOT scalability.