Decoding Schedule Research Articles

Integer programming‐based non‐uniform window decoding schedules for spatially coupled low‐density parity‐check codes

Spatially coupled low-density parity-check (SC-LDPC) codes generally use a window decoding scheme, which is known to yield a near-optimal decoding, compared to full block decoding. Recently, a non-uniform schedule has been proposed to eliminate unnecessary updates of variable nodes within a window: this schedule is generated based on the behaviour of variable node updates analysed by density evolution. Here, the authors present a new non-uniform schedule based on integer programming, whereby the objective functions and constraints are derived from a protograph-based extrinsic information transfer chart. Our design is more flexible than the previous design, because the integer programming-based design allows reduction of update numbers and performance losses through the constraints function, whereas the previous design requires observation of variable node update behaviour. The authors report the performance of their designs of non-uniform schedules in additive white Gaussian noise (AWGN) and inter-symbol interference (ISI) channels. Particularly, in the ISI channel, the authors’ non-uniform schedules are designed with cooperative decoding between a Bahl-Cocke-Jelinek-Raviv (BCJR) detector and an SC-LDPC decoder.

Design of Bilayer and Multi-Layer LDPC Ensembles From Individual Degree Distributions

A new approach for designing bilayer and multi-layer LDPC codes is proposed and studied in the asymptotic regime. The ensembles are defined through individual uni-variate degree distributions, one for each layer. We present a construction that: 1) enables low-complexity decoding for high-SNR channel instances, 2) provably approaches capacity for low-SNR instances, 3) scales linearly (in terms of design complexity) in the number of layers. For the setup where decoding the second layer is significantly more costly than the first layer, we propose an optimal-cost decoding schedule and study the trade-off between code rate and decoding cost.

LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.

Fast Column Message-Passing Decoding of Low-Density Parity-Check Codes

A new fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated in this brief. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The architecture is synthesized using the TSMC 40 nm CMOS technology node and operates at a clock frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps while consuming 72 mW of power. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder.

Belief-Propagation Decoding of LDPC Codes With Variable Node–Centric Dynamic Schedules

Belief propagation (BP) decoding of low-density parity-check (LDPC) codes with various dynamic decoding schedules have been proposed to improve the efficiency of the conventional flooding schedule. As the ultimate goal of an ideal LDPC code decoder is to have correct bit decisions, a dynamic decoding schedule should be variable node (VN)-centric and be able to find the VNs with probable incorrect decisions and having a good chance to be corrected if chosen for update. We propose a novel and effective metric called conditional innovation (CI) which serves this design goal well. To make the most of dynamic scheduling which produces high-reliability bit decisions, we limit our search for the candidate VNs to those related to the latest updated nodes only. Based on the CI metric and the new search guideline separately or in combination, we develop several highly efficient decoding schedules. To reduce decoding latency, we introduce multi-edge updating versions which offer extra latency-performance tradeoffs. Numerical results show that both single-edge and multi-edge algorithms provide better decoding performance against most dynamic schedules and the CI-based algorithms are particularly impressive at the first few decoding iterations.

Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

Low-Complexity Concatenated LDPC-Staircase Codes

A low-complexity soft-decision concatenated FEC scheme, consisting of an inner LDPC code and an outer staircase code is proposed. The inner code is tasked with reducing the bit error probability below the outer-code threshold. The concatenated code is obtained by optimizing the degree distribution of the inner-code ensemble to minimize estimated data-flow, for various choices of outer staircase codes. A key feature that emerges from this optimization is that it pays to leave some inner codeword bits completely uncoded, thereby greatly reducing a significant portion of the decoding complexity. The trade-off between required SNR and decoding complexity of the designed codes is characterized by a Pareto frontier. Computer simulations of the resulting codes reveals that the net coding-gains of existing designs can be achieved with up to 71\% reduction in complexity. A hardware-friendly quasi-cyclic construction is given for the inner codes, which can realize an energy-efficient decoder implementation, and even further complexity reductions via a layered message-passing decoder schedule.

Non-Uniform Window Decoding Schedules for Spatially Coupled LDPC Codes

Spatially coupled low-density parity-check codes can be decoded using a graph-based message passing algorithm applied across the total length of the coupled graph. However, considering practical constraints on decoding latency and complexity, a sliding window decoding approach is normally preferred. In order to reduce decoding complexity compared with standard parallel decoding schedules, serial schedules can be applied within a decoding window. However, uniform serial schedules within a window do not provide the expected reduction in complexity. Hence, we propose non-uniform schedules (parallel and serial) based on measured improvements in the estimated bit error rate (BER). We show that these non-uniform schedules result in a significant reduction in complexity without any loss in performance. Furthermore, based on observations made using density evolution, we propose a non-uniform pragmatic decoding schedule (parallel and serial) that does not require any additional calculations (e.g., BER estimates) within the decoding process.

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

Decoding schedule generating method for successive‐cancellation decoder of polar codes

Successive cancellation (SC) is the first and widely known decoder of polar codes, which has received a lot of attentions. However, its decoding schedule generating methods are still primitive. Based on a newly found factor, this study proposes an online method to generate the decoding schedule of SC decoder by a non-recursive way. The decoding schedule of SC decoder includes two parts. One is to determine which of likelihood ratios (LRs) can be shared and which of LRs need to be calculated. The other is to select a calculation formula for a LR to be computed. As shown by the comparisons among the proposed method and existing methods, the proposed method solves the first part of the decoding schedule with constant critical path delay and lower space complexity, and solves the second part of the decoding schedule with less calculations. Besides, experimental results show that the proposed method does not affect the error performance of polar codes.

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2n-input network can be configured to support any 2i-input (0≤i≤n) network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130nm CMOS technology, the design achieves 384.3Mbps peak throughput at clock rate of 290MHz with 5.5 iterations. Consuming 4.02mm2 core area and 716mW power, the decoder has a 1.81bits/cycle/iteration/mm2 architecture efficiency and a 0.34nJ/bit/iteration energy efficiency, which is competitive with other recent works.

An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation

Polar codes have recently received a lot of attention because of their capacity-achieving performance and low encoding and decoding complexity. The performance of the successive cancellation decoder (SCD) of the polar codes highly depends on that of the partial-sum network (PSN) implementation. Hence, in this work, an efficient PSN architecture is proposed, based on the properties of polar codes. First, a new partial-sum updating algorithm and the corresponding PSN architecture are introduced which achieve a delay performance independent of the code length. Moreover, the area complexity is also reduced. Second, for a high-performance and area-efficient semi-parallel SCD implementation, a folded PSN architecture is presented to integrate seamlessly with the folded processing element architecture. This is achieved by using a novel folded decoding schedule. As a result, both the critical path delay and the area (excluding the memory for folding) of the semi-parallel SCD are approximately constant for a large range of code lengths. The proposed designs are implemented in both FPGA and ASIC and compared with the existing designs. Experimental result shows that for polar codes with large code length, the decoding throughput is improved by more than 1.05 times and the area is reduced by as much as 50.4%, compared with the state-of-the-art designs.

Multiple-Source Slepian-Wolf Coding Under a Linear Equation Correlation Model

In this work we present practical coding schemes for the problem of lossless distributed source coding for multiple sources. We consider two scenarios - the classical Slepian-Wolf case where there is no feedback from the terminal to the sources and a case where there is feedback from the terminal to the source encoders. The correlation model of interest is given by a system of linear equations, a generalization of the work of Stankovic et al. '06. We propose a transformation of correlation model and a way to determine proper decoding schedules, both of which are required to obtain the optimal sum rate. Our scheme allows us to exploit more correlations than those in the previous work. Simulation results show that the proposed coding scheme has lower sum rate than previous work in both scenarios.

DVB-T2 LDPC Decoder with Perfect Conflict Resolution

Currently most of LDPC decoders are implemented with the so-called layered algorithm for its implementation efficiency and relatively high decoding performance. However, not all of structured LDPC codes can be implemented with the layered algorithm directly because of the message updating conflicts within layers in the a-posteriori information memory. In this paper we focus on the resolution of this kind of conflicts for DVB-T2 LDPC decoders. Unlike the previous resolutions, we directly implement the layered algorithm without modifying the parity-check matrices (PCM) or the decoding algorithm. DVB-T2 LDPC decoder architecture is also proposed in this paper with two new techniques which guarantee conflict-free layered decoding. The PCM Rearrange technique reduces the number of conflicts and eliminates all of data dependency problems between layers to ensure high pipeline efficiency. The Layer Division technique deals with all remaining conflicts with a well-designed decoding schedule. Experiment results show that compared to state-of-the-art works we achieve a slight error-correcting performance gain for DVB-T2 LDPC codes.

A 115mW 1Gbps Bit-Serial Layered LDPC Decoder for WiMAX

Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24∼48 clock cycles per iteration for all the code rates defined in WiMAX standard. It occupies 3.36mm2 in SMIC 65nm CMOS process, and realizes 1056Mbps throughput at 1.2V, 110MHz and 10 iterations with 115mW power occupation, which infers a power efficiency of 10.9pJ/bit/iteration. The power efficiency is improved 63.6% in normalized comparison with the state-of-art WiMAX LDPC decoder.

Prioritized Information Recovery for Wireless Link-Layer Communication

In this paper we develop Prioritized Automatic Code Embedding (PACE) link-layer protocol to achieve preferred data recovery order across connections, while maintaining stable and reliable data flows over wireless networks. We classify link-layer traffic arrivals into different priorities based on the packet delay constraint and the distortion associated with the loss of that packet. The traffic arriving in each priority class is modeled as a poisson process. Consequently, we formulate the link-layer buffer as a multiclass M/G/1 priority queuing system where the decoding process (service process) of the PACE buffer is captured by a nonhomogeneous geometric distribution. This formulation enables the determination of an optimal dynamic decoding schedule for heterogeneous link-layer traffic arrivals. PACE employs a novel rate-adaptive Low Density Parity Check (LDPC) channel code for error recovery. We model the underlying LDPC decoding process and use it to determine an optimal code selection policy for maximal bandwidth utilization. We demonstrate experimentally that PACE reduces the throughput-delay cost by 20%-70% in comparison with the IEEE802.11 ARQ and Hybrid ARQ (HARQ) protocols. Further, the PACE protocol achieves 20%-60% improvement in channel bandwidth utilization and 2-10dB PSNR gain in realtime video quality.

New Optimizations for Layered Non-Binary LDPC Codes Decoding

Non-binary LDPC codes have interesting performances, especially for short to moderate blocklengths. The decoding schedule of these codes decoding, similarly to the binary case, has an important impact on the decoder's behaviour and should be carefully designed. This paper studies and optimizes the layered scheduling of non-binary LDPC codes following two approaches: A static approach, defining an optimized permanent scheduling for the decoder independently of its entries or state, and a dynamic approach adapting the scheduling on the fly following the decoder's convergence. These two approaches show either a reduction in the number of iterations of about 18% or a reduction in signal to noise ratio of about 0.05dB.

Construction and Hardware-Efficient Decoding of Raptor Codes

Raptor codes are a class of concatenated codes composed of a fixed-rate precode and a Luby-transform (LT) code that can be used as rateless error-correcting codes over communication channels. These codes have the atypical features of dynamic code-rate, highly irregular Tanner graph check-degree distribution, random LT-code structure, and LT-precode concatenation, which render a hardware-efficient decoder implementation achieving good error-correcting performance a challenging task. In this paper, the design of hardware-efficient Raptor decoders with good performance is addressed through joint optimizations targeting 1) the code construction, 2) decoding schedule, and 3) decoder architecture. First, random encoding is decoupled by developing a two-stage LT-code construction scheme that embeds structural features in the LT-graph that are amenable to efficient implementation while guaranteeing good performance. An LT-aware LDPC precode construction methodology that ensures architectural-compatibility with the structured LT code is also proposed. Second, a decoding schedule is optimized to reduce memory cost and account for processing workload-variability caused by the varying code rate. Third, to address the problems of check-degree irregularity and hardware underutilization, a novel reconfigurable check unit that attains a constant throughput while processing a varying number of LT and LDPC nodes is presented. These design steps collectively are employed to generate serial and partially-parallel decoder architectures. A Raptor code instance constructed using the proposed method having LT data-block length of 1210 is shown to outperform or closely match the performance of conventional LDPC codes over the code-rate range [0.4,2/3]. The corresponding hardware serial decoder is synthesized using 65-nm CMOS technology and achieves a throughput of 22 Mb/s at rate 0.4 for a BER of 10-6, dissipates an average power of 222 mW at 1.2 V, and occupies an area of 1.77mm2.

Adaptive Optimization of an Iterative Multiuser Detector for Turbo-Coded CDMA

Extrinsic information transfer (EXIT) charts are utilized to optimize the iterative multiuser detector receiver in a multiuser turbo-coded CDMA system. The (receive) power levels are optimized for the system load using a constrained nonlinear optimization approach. The optimal decoding schedule is derived dynamically using the power optimized EXIT chart and a Viterbi search algorithm. Dynamic scheduling is shown to be a more flexible approach which results in a more stable QoS for a typical system configuration than one-shot scheduling, and large complexity savings over a receiver without scheduling. We verify through simulations that complexity savings of over 50% and power savings of over 8dB can be achieved. We show that the optimized power levels combined with adaptive scheduling allows for efficient utilization of receiver resources for heavily loaded systems.

Construction and Iterative Decoding of LDPC Codes Over Rings for Phase-Noisy Channels

This paper presents the construction and iterative decoding of low-density parity-check (LDPC) codes for channels affected by phase noise. The LDPC code is based on integer rings and designed to converge under phase-noisy channels. We assume that phase variations are small over short blocks of adjacent symbols. A part of the constructed code is inherently built with this knowledge and hence able to withstand a phase rotation of 2π/M radians, where M is the number of phase symmetries in the signal set, that occur at different observation intervals. Another part of the code estimates the phase ambiguity present in every observation interval. The code makes use of simple blind or turbo phase estimators to provide phase estimates over every observation interval. We propose an iterative decoding schedule to apply the sum-product algorithm (SPA) on the factor graph of the code for its convergence. To illustrate the new method, we present the performance results of an LDPC code constructed over Z4 with quadrature phase shift keying (QPSK) modulated signals transmitted over a static channel, but affected by phase noise, which is modeled by the Wiener (random-walk) process. The results show that the code can withstand phase noise of 2° standard deviation per symbol with small loss.