Decoding Of LDPC Codes Research Articles

Intensity Reflection Coefficient Based Min-Sum Decoding for Low Density Parity Check Codes

AbstractLow Density Parity Check Codes (LDPC) give groundbreaking performance which is known to approach Shannon’s limits for sufficiently large block length. Historically and recently, LDPC have been known to give superior performance than concatenated coding. In the following paper, a proposal to modify the standard Min-Sum (MS) algorithm for decoding LDPC codes is presented. This is done by introduction of a factor, intensity reflection coefficient (IRC),

Low Complexity Weighted Reliability-Based Iterative Decoding of LDPC Codes

Low Complexity Weighted Reliability-Based Iterative Decoding of LDPC Codes

An Iterative LLR Derivation Algorithm Based on Extended Min-sum Decoding of Non-binary LDPC Codes

An Iterative LLR Derivation Algorithm Based on Extended Min-sum Decoding of Non-binary LDPC Codes

Hybrid decoding scheme based on WED and BF algorithms

This contribution studies the application of Weighting Erased Decoding (WED) algorithm in the decoding of LDPC codes. WED is a kind of maximum likelihood algorithm used in the decoding of linear block codes with quantized channel outputs. Based on WED algorithm and Bit Flipping (BF) algorithm, a hybrid decoding scheme is proposed, which takes advantage of the simplicity of BF and the utilizing of reliability of received symbols. Simulation results show that the proposed scheme is feasible and effective, but the performance improvement is limited and depends on a parameter similar to the minimum Hamming distance in block codes.Click

Some Results on MAP Decoding of Non-Binary LDPC Codes Over the BEC

In this paper, the transmission over the binary erasure channel (BEC) using non-binary LDPC (NBLDPC) codes is considered. The concept of peeling decoder and stopping sets is generalized to NBLDPC codes. Using these generalizations, a combinatorial characterization of decoding failures of NBLDPC codes is given, under assumption that the Belief Propagation (BP) decoder is used. Then, the residual ensemble of codes resulted by the BP decoder is defined and the design rate and the expectation of total number of codewords of the residual ensemble are computed. The decoding failure criterion combined with the density evolution analysis helps us to compute the asymptotic residual degree distribution for NBLDPC codes. Our approach to compute the residual degree distribution on the check node side is not efficient as it is based on enumeration of all the possible connections on the check node side which satisfy the decoding failure criterion. So, the computation of the asymptotic check node side residual degree distribution and further part of our analysis is performed for NBLDPC codes over GF2m with m = 2 . In order to show that asymptotically almost every code in such LDPC ensemble has a rate equal to the design rate, we generalize the argument of the Maxwell construction to NBLDPC codes, defined over GF22. It is also observed that, like in the binary setting, the Maxwell construction, relating the performance of MAP and BP decoding holds in this setting.

Interleaved Processing of Bit-Flipping Decoding For LDPC Codes

The BF decoding algorithm for LDPC codes is simple. However, if the number of burst errors is bigger than which BF algorithm can process, the decoding may fail. Interleaving technology is a kind of effective techniques to handle burst errors. Under this technology, consecutive errors in one codeword can be dispersed into multiple code words, therefore the number of errors in each codeword may be lower and in the range of processing ability of BF algorithm. Thence the interleaving technology in decoding can reduce the probability of correction failing and improve the transmission performance. In this paper, a class of burst channel has been studied and the interleaving is applied for data transmission. Simulation results show that the use of interleaving techniques can effectively reduce error rate.

An Iterative Decoding Algorithm with Backtracking to Lower the Error-Floors of LDPC Codes

Error-floors are the main reason for excluding LDPC codes from applications requiring very low bit-error rate. They are attributed to a particular structure in the codes' Tanner graphs, known as trapping sets, which traps the message-passing algorithms commonly used to decode LDPC codes, and prevents decoding from converging to the correct codeword. A technique is proposed to break trapping sets while decoding. Based on decoding results leading to a decoding failure, some bits are identified in a previous iteration and flipped and decoding is restarted. This backtracking may enable the decoder to get out of the trapped state. A semi-analytical method is also proposed to predict the error-floor after backtracking. Simulation results indicate the effectiveness of the proposed technique in lowering the error-floor. The technique, which has moderate complexity overhead, is applicable to any code without requiring a prior knowledge of the structure of its trapping sets.

Improved Linear Programming Decoding of LDPC Codes and Bounds on the Minimum and Fractional Distance

We examine LDPC codes decoded using linear programming (LP). Four contributions to the LP framework are presented. First, a new method of tightening the LP relaxation, and thus improving the LP decoder, is proposed. Second, we present an algorithm which calculates a lower bound on the minimum distance of a specific code. This algorithm exhibits complexity which scales quadratically with the block length. Third, we propose a method to obtain a tight lower bound on the fractional distance, also with quadratic complexity, and thus less than previously-existing methods. Finally, we show how the fundamental LP polytope for generalized LDPC codes and nonbinary LDPC codes can be obtained.

Achieving a near‐optimum erasure correction performance with low‐complexity LDPC codes

AbstractLow‐density parity‐check (LDPC) codes are shown to tightly approach the performance of idealized maximum distance separable (MDS) codes over memoryless erasure channels, under maximum likelihood (ML) decoding. This is possible down to low error rates and even for small and moderate block sizes. The decoding complexity of ML decoding is kept low thanks to a class of decoding algorithms, which exploit the sparseness of the parity‐check matrix to reduce the complexity of Gaussian elimination. ML decoding of LDPC codes is reviewed at first. A performance comparison among various classes of LDPC codes is then carried out, including a comparison with fixed‐rate Raptor codes for the same parameters. The results confirm that a judicious LDPC code design allows achieving a near‐optimum performance over the erasure channel, with very low error floors. Furthermore, it is shown that LDPC and Raptor codes, under ML decoding, provide almost identical performance in terms of decoding failure probability vs. overhead. Copyright © 2010 John Wiley & Sons, Ltd.

Low-complexity decoding for non-binary LDPC codes in high order fields

In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nm of values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ?(nm log2 nm). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.

Channel Modeling and Signal Processing for Probe Storage Channels

Probe-storage devices employ large arrays of probes to write/read data in parallel in some storage medium, and combine ultra-high density, low access times, and low power consumption. A particular probe-storage technique utilizes thermomechanical means to store and retrieve information in thin polymer films. In this paper, a system-level channel model for the thermomechanical probe-storage channel is presented. Each of the components of the proposed model is derived by extensive characterization of experimentally obtained readback signals from probe recording tests. Moreover, detection techniques that are actually utilized in a probe-storage prototype implementation are described, followed by coding techniques for added reliability in the presence of particles or other impurities of the storage medium. In addition to low-complexity coding constructs, a concatenated coding scheme with an outer LDPC and inner modulation code is considered, in order to establish a benchmark for overall system performance. A novel methodology for joint decoding of outer LDPC and inner (d,k) modulation codes is developed. Furthermore, an optimal soft decoder for the modulation code is proposed, based on a modification of the decoder metrics to accurately account for the probe storage channel output statistics. Experimental results are used throughout the paper to validate the channel model and identify its relevant parameters, as well as to verify the system performance obtained by simulations.

Low-floor decoders for LDPC codes

One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC code's Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than floors of the the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.

Memory-efficient and high-throughput decoding of quasi-cyclic LDPC codes

We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.

Two-staged informed dynamic scheduling for sequential belief propagation decoding of LDPC codes

Recent studies have shown that sequential belief propagation decoding of low-density parity-check codes can increase the decoding convergence speed while simultaneously improving the asymptotic performance compared to the conventional flooding scheme. Two of the practical sequential decoding schemes known are the ones by Casado et al. (2007) in which informed dynamic scheduling is used for scheduling the sequential updates of the messages. In this letter, we propose a two-staged informed dynamic scheduling that unifies and outperforms the two schemes of Casado et al.

Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes"

This is a comment article on the publication "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes" Rovini et al. (2009). We mention that there has been similar work reported in the literature before, and the previous work has not been cited correctly, for example Gunnam et al. (2006, 2007). This brief note serves to clarify these issues.

Reply to “Comments on Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes”

This is a reply to the comments by Gunnam et al. "Comments on 'Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes'", EURASIP Journal on Embedded Systems, vol. 2009, Article ID 704174 on our recent work "Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes", EURASIP Journal on Embedded Systems, vol. 2009, Article ID 723465.

Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes

We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.

Computationally efficient decoding of LDPC codes

A computationally efficient algorithm for the decoding of low-density parity check codes is introduced. Instead of updating all bit and check nodes at each decoding iteration, the developed algorithm only updates unreliable check and bit nodes. A simple reliability criteria is developed to determine the active bit and check nodes per decoding iteration. Based on the developed technique, significant computation reductions are achieved with very little or no loss in the BER performance of the LDPC codes. The proposed method can be implemented with a slight modification to the sum–product algorithm with negligible additional hardware complexity.

Multiple Scaling Extrinsic Soft Information for Improved Min-Sum Iterative Decoding of LDPC Codes

This paper presents an improved min-sum iterative decoding scheme for regular and irregular LDPC codes. The proposed decoding scheme scales the extrinsic soft information from variable nodes to check. Different scaling factors are applied for iterations and the scaling factors are obtained by a simplified vector optimization method.

Generalised reliability‐based syndrome decoding of LDPC codes

AbstractAimed at bridging the gap between the maximum likelihood and the suboptimal decoding schemes for short or medium LDPC codes, a generalised ordered statistic decoding (OSD), in the form of syndrome decoding, is presented in the paper. The OSD is invoked once when a nonzero decoding syndrome is returned for the preceded belief propagation (BP) or min‐sum (MS) variants. With respect to the OSD with an accumulative reliability metric for the BP in the logarithmic likelihood ratio (LLR) domain, we extend the metric to the BP in the probability domain. Furthermore, the OSD with the metric specific for the MS variants, shows an appealing trade‐off between performance and complexity. Meanwhile, when determining the optimal error pattern estimation, an alternative designed to reduce the number of the required real additions proves to be effective. Copyright © 2008 John Wiley & Sons, Ltd.