Decoding Engine Research Articles

유럽형 지상파/케이블/위성 멀티모드 HD 방송 수신이 가능한 통합 수신기 구현

This paper presents an integrated receiver to support multimode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The integrated receiver consists of a tuner block, a receiver engine, a frame processor, and an A/V decoder. The receiver engine includes a channel decoding engine and a demodulation engine to perform OFDM and APSK demodulations. The frame processor performs deinterleaving and BB frame decoding functions. The demodulator engine and the frame processor are implemented in two FPGA devices and DSP-based embedded software, respectively. To verify the functionality of the integrated receiver, it is tested in the laboratory. Commercial PC-based modulators are used to generate the DVB-T2, DVB-C2, and DVB-S2 modulated signals. The integrated receiver was tested under various operation modes as specified in the standards such as DVB-T2, DVB-C2, and DVB-S2 and showed successful operation in all the scenarios tested.

Area and energy efficient 802.11ad LDPC decoding processor

The design of multi-Gbit/s low-density parity-check code (LDPC) decoders has become a hot topic in recent years to meet the growing demand of the transformation towards 4G. An area and energy efficient multi-Gbit/s LDPC decoder engine with a fully paralleled layered architecture based on an application-specific instruction set processor (ASIP) using Synopsys IP designer is presented. When the ASIP core is instantiated for 802.11ad, it achieved a throughput of up to 7 Gbit/s at three iterations with a latency of 95 ns, a record energy efficiency of 2.5 pJ/bit/iteration and an area efficiency of 54.5 Gbit/s/sq-m in CMOS 28 nm technology for the 1/2 rate, showing it to be competitive against published ASIC solutions.

Energy-aware decoder management: a case study on RVC-CAL specification based on just-in-time adaptive decoder engine

Motivated by the pervasive use of multimedia applications in battery-powered portable devices, the latest video coding standards have been developed to enable higher data compression rates and decoding efficiencies. An MPEG Reconfigurable Video Coding (RVC) framework has been proposed to efficiently support multiple codec specifications and facilitate innovation in codec design. At the same time, an energy-aware design is expected to be included in video coding standards for the purpose of energy optimization of multimedia applications, which are known to create high computational loads. This paper proposes an energy-aware decoder manager based jointly on a Just-In-Time Adaptive Decoder Engine (Jade) and an energy estimation model. The model is driven by Performance Monitoring Counters (PMCs) and is fitted by the multivariate adaptive regression splines (MARS) method. The estimation results achieve average relative errors of less than 10%. In addition, the maximal model computation overhead is 4.58%. By combining the estimation model into the RVC framework, the experimental results show good potential for energy efficiency improvement with increases of up to 21.8% based on energy considerations.

Novel LVCSR Decoder Based on Perfect Hash Automata and Tuple Structures – SPREAD –

The paper presents the novel design of a one-pass large vocabulary continuous-speech recognition decoder engine, named SPREAD. The decoder is based on a time-synchronous beam-search approach, including statically expanded cross-word triphone contexts. An approach using efficient tuple structures is proposed for the construction of the complete search-network. The foremost benefits are the important space savings and higher processing speed, and the compact and reduced size of the tuple structure, especially when exploiting the structure of the key. In this way, the time needed to load the ASR search-network into the memory is also significantly reduced. Further, the paper proposes and presents the complete methodology for compiling general ASR knowledge sources into a tuple structures. Additionally, the beam search is enhanced with the novel implementation of a bigram language model Look-Ahead technique, by using tuple structures and a caching scheme. The SPREAD LVCSR decoder is based on a token-passing algorithm, capable of restricting its search-space by several types of token pruning. By using the presented language model Look-Ahead technique, it is possible to increase the number of tokens that can be pruned without decoding precision loss.

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

Incorporating packet semantics in scheduling of real-time multimedia streaming

In this work, we develop a novel packet scheduling algorithm that properly incorporates the semantics of a packet. We find that improvement in overall packet loss does not necessarily coincide with improvement in user perceivable QoS. The objective of this work is to develop a packet scheduling mechanism which can improve the user perceivable QoS. We do not focus on improving packet loss, delay, or burstiness. We develop a metric called, "Packet Significance," that effectively quantifies the importance of a packet that properly incorporates the semantics of a packet from the perspective of compression. Packet significance elaborately incorporates inter-frame, intra-frame information dependency, and the transitive information dependency characteristics of modern compression schemes. We apply packet significance in scheduling the packet. In our context, packet scheduling consists of two technical ingredients: packet selection and interval selection. Under limited network bandwidth availability, it is desirable to transmit the subset of the packets rather than transmitting the entire set of packets. We use a greedy approach in selecting packets for transmission and use packet significance as the selection criteria. In determining the transmission interval of a packet, we incorporate the packet significance. Simulation based experiments with eight video clips were performed. We embed the decoding engine in our simulation software and examine the user perceivable QoS (PSNR). We compare the performance of the proposed algorithm with best effort scheduling scheme and one with simple QoS metric based scheduling scheme. Our Significance-Aware Scheduling scheme (SAPS) effectively incorporates the semantics of a packet and delivers best user perceivable QoS. SAPS can result in more packet loss or burstier traffic. Despite these limitations, SAPS successfully improves the overall user perceivable QoS.

A high-performance hardwired CABAC decoder for ultra-high resolution video

Context-Based Binary Arithmetic Coding (CABAC) is one of two entropy coders used in H.264/AVC, which achieves a high compression ratio at the expense of high computational complexity. For real-time decoding of ultra-high resolution video, we propose a high-throughput hardwired CABAC decoder subsystem. By analyzing the distribution of different types of syntax elements (SE), we propose a Two-Bin arithmetic decoding engine (Two-Bin AE) to generate two bins in one cycle for the most frequent SEs. In order to boost the utilization of the proposed engine, we employ a Prediction-Based Parallel Processing Method to perform decoding and context index calculation in parallel. Furthermore, we propose a Context Table Reallocation Scheme, which can shorten the critical path delay of a Two- Bin AE circuit by 18%. Experimental results show that our decoder on average takes only 118 clock cycles to decode one macroblock (MB) at Main Profile, Level 4.0. For QFHD, i.e., 4x1080 HD, sequences, it can run effectively at 110 MHz. The design has been successfully integrated into an H.264/AVC QFHD video decoder in an SOC system.

An efficient VLSI architecture for CBAC of AVS HDTV decoder

Context-based Binary Arithmetic Coding (CBAC) is a normative part of the newest X Profile of Advanced Audio Video coding Standard (AVS). This paper presents an efficient VLSI architecture for CBAC decoding in AVS. Compared with CBAC in H.264/AVC, the simpler binarization methods and context selection schemes are adopted in AVS. In order to avoid the slow multiplications, the traditional arithmetic calculation is transformed to the logarithm domain. Although these features can obtain better balance between the compression gain and implementation cost, it still brings huge challenge for high-throughput implementation. The fact that current bin decoding depends on previous bin results in long latency and limits overall system performance. In this paper, we present a software–hardware co-design by using bin distribution feature. A novel pipeline-based architecture is proposed where the arithmetic decoding engine works in parallel with the context maintainer. A finite state machine (FSM) is used to control the decoding procedure flexibly and the context scheduling is organized carefully to minimize the access times of context RAMs. In addition, the critical path is optimized for the timing. The proposed implementation can work at 150 MHz and achieve the real-time AVS CBAC decoding for 1080i HDTV video.

DSP-based multi-format video decoding engine for media adapter applications

There are four major components in a generic digital home framework: media center, set-top box, media adapter and portable viewer. In this paper, we present a DSP-based multi-format video decoding engine for realizing media adapter application. By choosing a powerful DSP core and designing an efficient and configurable software engine, the proposed solution is believed to possess low-cost and high-flexibility advantages at the same time. In our current implementation, the video decoding engine can decode most of the major video formats in the market, such as MPEG-1/2/4, H.264/AVC baseline/main, VC-I and its precedents, and some other MPEG-4-like formats. Simulation results demonstrate the efficiency of the decoding engine: videos up to SD resolution can be decoded seamlessly. The engine has been successfully integrated into an available media adapter module and the corresponding product. Our future work is to enhance the engine performance capable of handling HD contents.