Decoding Algorithm For Low-density Parity-check Research Articles

Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory

With the fast development of non-volatile storage technology, NAND flash memory faces more and more challenges such as data reliability and lifetime. To overcome the issue of the reliability, low-density parity-check (LDPC) codes are considered as a main candidate of error-correction-codes (ECCs) for NAND flash storages. However, conventional soft decoding algorithms for LDPC codes suffer from the drawback of slow convergence speed, which increases the decoding latency. For achieving fast convergence speed, a variable-node-based belief-propagation with message pre-processing (VNBP-MP) decoding algorithm for binary LDPC codes and a non-binary VNBP-MP (NVNBP-MP) decoding algorithm for non-binary LDPC codes are proposed. Both of the algorithms utilize the characteristics of the NAND flash channel to perform the message pre-processing operations. In theory, the propagation of unreliable messages can be effectively prevented and the propagation of reliable messages can be speeded up. To further improve the decoding convergence, the treatment for oscillating variable nodes is considered after the message pre-processing operations. The simulation results also show that the proposed algorithms both have a noticeable improvement in convergence speed and latency, without compromising error-correction performance, compared with the existing soft decoding algorithms.

LLR-Distribution-Based Non-Uniform Quantization for RBI-MSD Algorithm in MLC Flash Memory

Multi-level cell (MLC) technique has been widely used to improve the storage capacity of NAND flash memory at the price of sacrificing some storage reliability. As a type of excellent error-correction codes, low-density parity-check (LDPC) codes can significantly enhance the performance of flash memory. However, the conventional decoding algorithms for LDPC codes suffer from the drawback of high complexity. To address this problem, we propose a serial reliability-based iterative min-sum decoding (RBI-MSD) algorithm for LDPC-coded MLC flash memory systems to strike a desirable trade-off between the performance and complexity. Furthermore, we conceive a novel log-likelihood-ratio (LLR)-distribution-based non-uniform quantization method for the RBI-MSD algorithm. Unlike conventional quantization methods, the proposed non-uniform quantization method substantially exploits the distribution characteristics of channel initial LLRs in MLC flash memory. Simulation results indicate that the proposed non-uniform quantization method not only exhibits more excellent error performance than the conventional non-uniform and uniform counterparts, but also is applicable to other RBI decoding algorithms.

A modified normalized min-sum algorithm for LDPC decoding using order statistics

In this paper, we propose a new modified normalized min-sum algorithm for low-density parity-check decoding. Instead of normalizing the results of the check node renew calculations by a single modification factor, we use two different modification factors to normalize the results of check node renew calculations. One modification factor for the position of the first minimum value and another modification factor for other positions. We obtain two modification factors by theoretical analysis using the theory of order statistics. Simulation results show that the new modified normalized min-sun algorithm achieves better bit error rate performance than normalized min-sun algorithm without adding implementation complexity. Copyright © 2016 John Wiley & Sons, Ltd.

Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding

To increase the quality of wireless transmission, wireless communication systems employ advanced forward error correction codes such as turbo codes and low-density parity-check (LDPC) codes. To achieve smooth transition between turbo and LDPC decoding in different communication standards, we propose a VLSI design of a multimode radix-4 soft-input soft-output (SISO) kernel in this paper. The proposed radix-4 SISO kernel composed of three recursive processing elements alternatively employs a radix-4 forward–backward algorithm for LDPC decoding and a radix-4 single-binary/double-binary enhanced max-log-maximum a posteriori probability algorithm for turbo decoding by efficiently sharing computational units. The proposed radix-4 SISO kernel achieves an area reduction of 21.8% when compared with the uncombined SISO kernels for alternatively decoding the turbo and LDPC codes. The proposed radix-4 SISO kernel is verified by implementing it in an application-specific integrated circuit of 0.45 $\mathrm{mm}^{2}$ core area by using a 90-nm CMOS process with a maximum area efficiency of 10.65 bits/ $\mathrm{mm}^{2}$ . In addition, the throughput rates of the long-term evolution and worldwide interoperability for microwave access schemes for both LDPC and turbo decoding can be achieved using eight proposed radix-4 SISO kernels.

New Min-sum LDPC Decoding Algorithm Using SNR-Considered Adaptive Scaling Factors

This paper proposes a new min-sum algorithm for low-density parity-check decoding. In this paper, we first define the negative and positive effects of the received signal-to-noise ratio (SNR) in the min-sum decoding algorithm. To improve the performance of error correction by considering the negative and positive effects of the received SNR, the proposed algorithm applies adaptive scaling factors not only to extrinsic information but also to a received log-likelihood ratio. We also propose a combined variable and check node architecture to realize the proposed algorithm with low complexity. The simulation results show that the proposed algorithm achieves up to 0.4 dB coding gain with low complexity compared to existing min-sum-based algorithms.

Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes

We propose a non-binary stochastic decoding algorithm for low-density parity-check (LDPC) codes over GF(q) with degree two variable nodes, called Adaptive Multiset Stochastic Algorithm (AMSA). The algorithm uses multisets, an extension of sets that allows multiple occurrences of an element, to represent probability mass functions that simplifies the structure of the variable nodes. The run-time complexity of one decoding cycle using AMSA is O(q) for conventional memory architectures, and O(1) if a custom memory architecture is used. Two fully-parallel AMSA decoders are implemented on FPGA for two (192,96) (2,4)-regular codes over GF(64) and GF(256), both achieving a maximum clock frequency of 108 MHz. The GF(64) decoder has a coded throughput of 65 Mb/s at Eb/N0=2.4 dB when using conventional memory, while a decoder using the custom memory version can achieve 698 Mb/s at the same Eb/N0. At a frame error rate (FER) of 2×10-6 the GF(64) version of the algorithm is only 0.04 dB away from the floating-point SPA performance, and for the GF(256) code the difference is 0.2 dB. To the best of our knowledge, this is the first fully parallel non-binary LDPC decoder over GF(256) reported in the literature.

Hybrid Linear Programming Based Decoding Algorithm for LDPC Codes

This paper presents a hybrid decoding algorithm for low-density parity-check (LDPC) codes based on the interior point method with barrier function for linear programming (LP) decoding introduced by Wadayama . First, an efficient implementation of Wadayama's algorithm is presented. The main idea behind the modification is to approximate the barrier function for the fundamental polytope defining the code so that it contains only one linear constraint for each of the parity-check constraints. A two-stage hybrid decoding which combines the interior point decoding and a low-complexity decoding algorithm for LDPC codes is then proposed. Simulation results show that the approximations introduced in the proposed algorithms do not result in any performance degradation, while considerably reducing the decoding complexity and latency.

Replica horizontal-shuffled iterative decoding of low-density parity-check codes

For practical considerations, it is essential to accelerate the convergence speed of the decoding algorithm used in an iterative decoding system. In this paper, replica versions of horizontal-shuffled decoding algorithms for low-density parity-check (LDPC) codes are proposed to improve the convergence speed of the original versions. The extrinsic information transfer (EXIT) chart technique is extended to the proposed algorithms to predict their convergence behavior. Both EXIT chart analysis and numerical results show that replica plain horizontal-shuffled (RPHS) decoding converges much faster than both plain horizontal-shuffled (PHS) decoding and the standard belief-propagation (BP) decoding. Furthermore, it is also revealed that replica group horizontal-shuffled (RGHS) decoding can increase the parallelism of RPHS decoding as well as preserve its high convergence speed if an equivalence condition is satisfied, and is thus suitable for hardware implementation.

A Method for Grouping Symbol Nodes of Group Shuffled BP Decoding Algorithm

In this paper, we propose a method for enhancing performance of a sequential version of the belief-propagation (BP) decoding algorithm, the group shuffled BP decoding algorithm for low-density parity-check (LDPC) codes. An improved BP decoding algorithm, called the shuffled BP decoding algorithm, decodes each symbol node in serial at each iteration. To reduce the decoding delay of the shuffled BP decoding algorithm, the group shuffled BP decoding algorithm divides all symbol nodes into several groups. In contrast to the original group shuffled BP, which automatically generates groups according to symbol positions, in this paper we propose a method for grouping symbol nodes which generates groups according to the structure of a Tanner graph of the codes. The proposed method can accelerate the convergence of the group shuffled BP algorithm and obtain a lower error rate in a small number of iterations. We show by simulation results that the decoding performance of the proposed method is improved compared with those of the shuffled BP decoding algorithm and the group shuffled BP decoding algorithm.

Sequential message-passing decoding of LDPC codes by partitioning check nodes

In this paper, we analyze the sequential message- passing decoding algorithm of low-density parity-check (LDPC) codes by partitioning check nodes. This decoding algorithm shows better bit error rate (BER) performance than the conventional message-passing decoding algorithm, especially for the small number of iterations. Analytical results indicate that as the number of partitioned subsets of check nodes increases, the BER performance is improved. We also derive the recursive equations for mean values of messages at check and variable nodes by using density evolution with a Gaussian approximation. From these equations, the mean values are obtained at each iteration of the sequential decoding algorithm and the corresponding BER values are calculated. They show that the sequential decoding algorithm converges faster than the conventional one. Finally, the analytical results are confirmed by the simulation results.

Variable non-uniform quantized belief propagation algorithm for LDPC decoding

Non-uniform quantization for messages in Low-Density Parity-Check (LDPC) decoding can reduce implementation complexity and mitigate performance loss. But the distribution of messages varies in the iterative decoding. This letter proposes a variable non-uniform quantized Belief Propagation (BP) algorithm. The BP decoding is analyzed by density evolution with Gaussian approximation. Since the probability density of messages can be well approximated by Gaussian distribution, by the unbiased estimation of variance, the distribution of messages can be tracked during the iteration. Thus the non-uniform quantization scheme can be optimized to minimize the distortion. Simulation results show that the variable non-uniform quantization scheme can achieve better error rate performance and faster decoding convergence than the conventional non-uniform quantization and uniform quantization schemes.

Degree-Matched Check Node Decoding for Regular and Irregular LDPCs

This brief examines different parity-check node decoding algorithms for low-density parity-check (LDPC) codes, seeking to recoup the performance loss incurred by the min-sum approximation compared to sum-product decoding. Two degree-matched check node decoding approximations that depend on the check node degree d <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> are presented. Both have low complexity and can be applied to any degree distribution. Simulation results show near sum-product decoding performance for both degree-matched check node approximations for regular and irregular LDPCs

Reduced-Complexity Decoding of LDPC Codes

Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives.

Threshold Values and Convergence Properties of Majority-Based Algorithms for Decoding Regular Low-Density Parity-Check Codes

This work presents a detailed study of a family of binary message-passing decoding algorithms for low-density parity-check (LDPC) codes, referred to as algorithms. Both Gallager's algorithm A (G/sub A/) and the standard majority decoding algorithm belong to this family. These algorithms, which are, in fact, the building blocks of Gallager's algorithm B (G/sub B/), work based on a generalized majority-decision rule and are particularly attractive for their remarkably simple implementation. We investigate the dynamics of these algorithms using density evolution and compute their (noise) threshold values for regular LDPC codes over the binary symmetric channel. For certain ensembles of codes and certain orders of majority-based algorithms, we show that the threshold value can be characterized as the smallest positive root of a polynomial, and thus can be determined analytically. We also study the convergence properties of majority-based algorithms, including their (convergence) speed. Our analysis shows that the stand-alone version of some of these algorithms provides significantly better performance and/or convergence speed compared with G/sub A/. In particular, it is shown that for channel parameters below threshold, while for G/sub A/ the error probability converges to zero exponentially with iteration number, this convergence for other majority-based algorithms is super-exponential.