Decoding Of Low-density Parity-check Codes Research Articles

Design of DNA Storage Coding Scheme With LDPC Codes and Interleaving.

In this paper, we propose a new coding scheme for DNA storage using low-density parity-check (LDPC) codes and interleaving techniques. While conventional coding schemes generally employ error correcting codes in both inter and intra-oligo directions, we show that inter-oligo LDPC codes, optimized by differential evolution, are sufficient in ensuring the reliability of DNA storage due to the powerful soft decoding of LDPC codes. In addition, we apply interleaving techniques for handling non-uniform error characteristics of DNA storage to enhance the decoding performance. Consequently, the proposed coding scheme reduces the required number of oligo reads for perfect recovery by 26.25% ~ 38.5% compared to existing state-of-the-art coding schemes. Moreover, we develop an analytical DNA channel model in terms of non-uniform binary symmetric channels. This mathematical model allows us to demonstrate the superiority of the proposed coding scheme while isolating the experimental variation, as well as confirm the independent effects of LDPC codes and interleaving techniques.

Design and analysis of stochastic 5G new radio LDPC decoder using adaptive sparse quantization kernel least mean square algorithm for optical satellite communications

AbstractA Stochastic Low‐Density Parity‐Check (LDPC) decoder is a type of 5G New Radio standard LDPC decoder that uses stochastic techniques to perform decoding. Stochastic LDPC decoding with 5G NR standard typically uses an iterative process, where messages exchanged among variable nodes (VN), check nodes multiple times. Stochastic LDPC decoders are often used in scenarios where the received signal is subject to varying levels of noise. They will provide improved error correction performance compared to traditional LDPC decoders, especially when dealing with channels with varying signal‐to‐noise ratios in 5G networks. Using the adaptive sparse quantization kernel least mean square algorithm (SLDPC‐ASQ‐KLMSA), this paper proposes an area‐efficient architecture design for a stochastic LDPC decoder. The LDPC code (2048, 1723) is taken from the LOGBASE‐T standard and used in this study. We examine the ASQ‐KLMSA connection effects. Starting with the VN. It makes checking node functioning easier and reduces inter‐connect complexity by capping extrinsic message length at 2 bits. Because of the simplified check node operation in ASQ‐KLMSA, the decoder nodes must exchange messages with a greater degree of accuracy. The 3–3 input grouping sub‐node of the degree‐6 VN was changed with an adder‐based 5–1 input grouping sub‐node for the (2048, 1723) code in order to get more accurate results when the check‐to‐variable messages aren't strong enough. A suggested decoder architecture was determined using a stochastic LDPC decoder developed for TSMC 65 nm process (2048, 1723). Bite error rate, throughput, mean square error, latency, power, and area usage are some of the metrics used to evaluate the effectiveness of the SLDPC‐ASQ‐KLMSA algorithm that has been suggested and implemented in Python. Thus, the proposed approach has attained 34.44%, and 38.39% low mean square error while compared with the existing methods such as higher‐performance stochastic LDPC decoder architecture designed through correlation analysis (HP‐SLDPC‐CA), Higher Throughput and Hardware Efficient Hybrid LDPC Decoder Utilizing Bit‐Serial Stochastic Updating(HLDPC‐BSSU), Flexible FPGA‐Based Stochastic Decoder for 5G LDPC codes (FPGA‐SD‐5G‐LDPC), respectively.

Decoding LDPC Codes by Using Negative Proximal Regularization

The low-density parity-check (LDPC) decoding problem can be expressed as an integer linear programming (ILP) problem. One efficient method to solve the ILP problem is to relax the integer constraints and add penalty terms to the objective function, and the revised problem can be solved via the alternating direction method of multipliers (ADMM) algorithm. These penalty terms can punish the non-integral solutions and improve the decoding performance of the decoder. However, ADMM decoders are easily trapped in a local solution, which limits the frame error rate (FER) performance of the decoders at low signal-to-noise ratios (SNR). In this paper, we propose a restartable ADMM-based decoder using a negative proximal regularization. The negative proximal term will be updated whenever the decoder finds a new local solution. Therefore, the decoder can be restarted several times and the candidate solution which satisfies the parity-check equations and has the lowest objective function value can be selected as the decoder’s output. Some properties, together with several choices of penalty terms are discussed. We also investigate the convergence of our proposed decoder, and prove that the possibility of decoding errors is independent of the codeword that is transmitted. Simulation results show that our proposed decoder outperforms other ADMM-based decoders in most cases, while the decoding complexity maintains the same.

An investigation of low-density parity-check codes and polar codes for future communication systems

In the fifth-generation (5G) era and future, mobile internet and internet of things (IoT) are the driving forces for mobile communications’ development. The three main 5G usage scenarios: enhanced mobile broadband (eMBB), massive machine-type communication (mMTC), and ultra-reliable and low-latency communications (URLLC), require improvement in throughput, reliability, and latency as compared with the previous fourth generation (4G) system. In this paper, an investigation is done on the coding part of the wireless communication systems. Two channel coding types; low-density parity-check (LDPC) code which is used as the coding scheme for data transmission, and Polar code which is utilized for control in 5G are discussed. Moreover, simulations are performed to assess their performance. The simulation results revealed the superiority of polar code for transmitting short information messages and LDPC for transmitting long data messages. The use of LDPC and polar codes in 5G communication systems is justified by their ability to accommodate a wide range of data lengths and code rates, as well as their good bit error rate (BER) performance. Furthermore, the effect of the number of iterations on the BER performance of LDPC code and different decoding algorithms of polar code are considered.

Model-Driven Deep Learning ADMM Decoder for Irregular Binary LDPC Codes

In this letter, a model-driven deep learning (DL) decoder for irregular binary low-density parity-check (LDPC) codes is proposed via the alternating direction method of multipliers (ADMM) technique. Our technical contributions three twofold: 1) we formulate the maximum likelihood decoding problem as a non-convex quadratic program with a new penalty term and present an ADMM based decoder; 2) to alleviate hyper-parameter tuning, we employ the deep unfolding strategy to derive a model-driven ADMM-DL decoder; and 3) to save the number of learning parameters, we propose an initialization strategy which can apply to different codeword structures. Specifically, the designing procedure for the DL network structure and DL network parameters training algorithm are presented in detail for efficient implementation. Numerical results demonstrate that the proposed model-driven ADMM-DL decoder for irregular binary LDPC codes is competitive in comparison with the state-of-the-arts.

Low-density parity-check codes: Highway to channel capacity

Low-density parity-check (LDPC) codes are not only capacity-approaching, but also greatly suitable for high-throughput implementation. Thus, they are the most popular codes for high-speed data transmission in the past two decades. Thanks to the low-density property of their parity-check matrices, the optimal maximum a posteriori probability decoding of LDPC codes can be approximated by message-passing decoding with linear complexity and highly parallel nature. Then, it reveals that the approximation has to carry on Tanner graphs without short cycles and small trapping sets. Last, it demonstrates that well-designed LDPC codes with the aid of computer simulation and asymptotic analysis tools are able to approach the channel capacity. Moreover, quasi-cyclic (QC) structure is introduced to significantly facilitate their high-throughput implementation. In fact, compared to the other capacity-approaching codes, QC-LDPC codes can provide better area-efficiency and energy-efficiency. As a result, they are widely applied in numerous communication systems, e.g., Landsat satellites, Chang'e Chinese Lunar mission, 5G mobile communications and so on. What's more, its extension to non-binary Galois fields has been adopted as the channel coding scheme for BeiDou navigation satellite system.

Implementation of encoder and decoder for low-density parity-check codes in continuous-variable quantum key distribution on a field programmable gate array

Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, ∼0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps decoding throughput was achieved, better than the theoretical key rate of prototype of CVQKD.

A Simple Check Polytope Projection Penalized Algorithm for ADMM Decoding of LDPC Codes

ADMM penalized decoding method for Low-Density Parity-Check (LDPC) Codes can improve the frame error rate (FER) performance than the standard ADMM decoder by adding penalty terms to the objective function. However, penalty parameter optimization of the penalty terms is very difficult and extremely time-consuming. Additionally, the Euclidean projection onto the check polytope is the most complex part of ADMM-based decoding algorithms. In this paper, by dynamically choosing even-vertex in the check polytope closest to the input vector as the approximate projection, a simple and novel check polytope projection penalized algorithm for ADMM decoding is proposed which can avoid the tedious work of penalty parameter optimization and simplify the check polytope projection. The simulation results show that the proposed algorithm can substantially reduce the projection time while achieving better FER performance when compared with the existing penalized decoding. In particular, the proposed algorithm can save the decoding time by 23% to 41% compared with ADMM-PD-LSA algorithm.

PDD-Based Decoder for LDPC Codes With Model-Driven Neural Networks

In this work, we develop a double-loop iterative decoding algorithm for low density parity check (LDPC) codes based on the penalty dual decomposition (PDD) framework. We utilize the linear programming (LP) relaxation and the penalty method to handle the discrete constraints and the over-relaxation method is employed to improve convergence. Then, we unfold the proposed PDD decoding algorithm into a model-driven neural network, namely the learnable PDD decoding network (LPDN). We turn the tunable coefficients and parameters in the proposed PDD decoder into layer-dependent trainable parameters which can be optimized by gradient descent-based methods during network training. Simulation results demonstrate that the proposed LPDN with well-trained parameters is able to provide superior error-correction performance with much lower computational complexity as compared to the PDD decoder.

Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT

As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low signal-to-noise ratios (SNRs) with negligible decoding performance loss.

A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols

A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols

Decoding Nonbinary LDPC Codes via Proximal-ADMM Approach

In this paper, we focus on decoding nonbinary low-density parity-check (LDPC) codes in Galois fields of characteristic two via the proximal alternating direction method of multipliers (proximal-ADMM). By exploiting Flanagan/Constant-Weighting embedding techniques and the decomposition technique based on three-variables parity-check equations, two efficient proximal-ADMM decoders for nonbinary LDPC codes are proposed. We show that both of them are theoretically guaranteed convergent to some stationary point of the decoding model and either of their computational complexities in each proximal-ADMM iteration scales linearly with LDPC code’s length and the size of the considered Galois field. Moreover, the decoder based on the Constant-Weight embedding technique satisfies the favorable property of codeword symmetry. Simulation results demonstrate their effectiveness in comparison with state-of-the-art LDPC decoders.

Adaptive Belief Propagation Decoding of CRC Concatenated NR LDPC and Polar Codes

In this paper, we propose a modified adaptive belief propagation (ABP) algorithm, which is referred to as the random ABP (R-ABP) algorithm, for decoding short channel codes adopted in the fifth generation (5G) New Radio (NR) wireless systems. Based on the cyclic redundancy check (CRC) concatenation structure of 5G channel codes, we can take partial or even all CRC bits into iterative R-ABP decoding to improve the error correction performance, while the error detection capability can still be guaranteed by the remaining CRC bits and a proposed threshold-based acceptance criterion. We call this improved R-ABP decoding the threshold-and-CRC-aided R-ABP (TCA-R-ABP) decoding. The simulation results show that our proposed TCA-R-ABP algorithm outperforms the state-of-the-art decoding algorithms for many 5G low-density parity-check (LDPC) and polar codes. Moreover, the proposed TCA-R-ABP algorithm leads to a unified decoder for LDPC and polar codes, which has the potential to be a lower-complexity decoder over the combination of the belief propagation (BP) and CRC-aided successive cancellation list (CA-SCL) decoders.

Automorphism Ensemble Decoding of Quasi-Cyclic LDPC Codes by Breaking Graph Symmetries

We consider automorphism ensemble decoding (AED) of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Belief propagation (BP) decoding on the conventional factor graph is equivariant to the quasi-cyclic automorphisms and therefore prevents gains by AED. However, by applying small modifications to the parity-check matrix at the receiver side, we can break the symmetry without changing the code at the transmitter. This way, we can leverage a gain in error-correcting performance using an ensemble of identical BP decoders, without increasing the worst-case decoding latency. The proposed method is demonstrated using LDPC codes from the CCSDS, 802.11n and 5G standards and produces gains of 0.2 to 0.3 dB over conventional BP decoding. Compared to the similarly performing saturated BP (SBP), the proposed algorithm reduces the average decoding latency by more than eight times.

Generalized Mutual Information-Maximizing Quantized Decoding of LDPC Codes With Layered Scheduling

In this paper, we propose a framework of the mutual information-maximizing (MIM) quantized decoding for low-density parity-check (LDPC) codes by using simple mappings and fixed-point additions. Our decoding method is generic in the sense that it can be applied to LDPC codes with arbitrary degree distributions, and can be implemented based on either the belief propagation (BP) algorithm or the min-sum (MS) algorithm. In particular, we propose the MIM density evolution (MIM-DE) to construct the lookup tables (LUTs) for the node updates. The computational complexity and implementation complexity are discussed and compared to the LUT decoder variants. To accelerate the convergence speed of decoding quasi-cyclic LDPC codes, we consider the layered schedule, and develop the layered MIM-DE to design the LUTs based on MS algorithm, leading to the MIM layered quantized MS (MIM-LQMS) decoder. An optimization method is further introduced to reduce the memory requirement for storing the LUTs. Simulation results show that the MIM quantized decoders outperform the state-of-the-art LUT decoders in the waterfall region with both 3-bit and 4-bit precision. Moreover, the 4-bit MIM-LQMS decoder can approach the error performance of the floating-point layered BP decoder within 0:1 dB.

Performance analysis of Min-Sum based LDPC decoder architecture for 5G new radio standards

A low-density parity-check code (LDPC) is one of the classical error-correcting code for message transmission over noisy channel. It meets desired Shannon limit performance and is adopted as a data channel for the 5th generation new radio (5G NR) standard. This paper investigates the LDPC decoder by applying minimum-sum (MS) algorithm on the base matrix (BG1) of 5G standards. The performance of the decoder such as bit-error-rate (BER) and frame-error-rate (FER) has been improved when the number of iterations increased for larger code word. The variable node and check node architecture based on the MS algorithm with pipelining stage has been implemented in the field programmable gate array (FPGA). Based on the implementation results, it is observed that the LDPC decoder shows better performance in throughput and hardware resource usage (HUE) with some additional look-up-tables (LUT) and flip-flops (FF).

On guaranteed correction of error patterns with artificial neural networks

In this paper, we analyze applicability of single-and two-hidden-layer feed-forward artificial neural networks, SLFNs and TLFNs, respectively, in decoding linear block codes. Based on the provable capability of SLFNs and TLFNs to approximate discrete functions, we discuss sizes of the network capable to perform maximum likelihood decoding. Furthermore, we propose a decoding scheme, which use artificial neural networks (ANNs) to lower the error-floors of low-density parity-check (LDPC) codes. By learning a small number of error patterns, uncorrectable with typical decoders of LDPC codes, ANN can lower the error-floor by an order of magnitude, with only marginal average complexity incense.

Fast LDPC GPU Decoder for Cloud RAN

The graphical processing unit (GPU), as a digital signal processing accelerator for cloud RAN, is investigated. This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> higher throughput compared to a recent GPU flooding decoder and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. For rapid deployment and flexibility, GPUs may be suitable as cloud RAN accelerators.

Neural Layered Decoding of 5G LDPC Codes

In this letter, we propose various low-complexity neural layered min-sum (NLMS) algorithms to improve the decoding performance of the fifth generation (5G) new radio (NR) low-density parity-check (LDPC) codes. Our proposals are based on the computationally-efficient normalized offset min-sum (NOMS) approach for the layered belief propagation (LBP). The main novelty of our proposals is a deep neural network (DNN) that implements the layered mode decoding and that additionally learns the normalization and the offset parameters of the NOMS scheme. The schemes that we propose use the DNN as well as adaptation and filtering for estimating the optimum values of these parameters. We show by simulation that our proposed decoders achieve a significant computational benefit compared to the standard (non-neural) LBP decoder without an appreciable performance penalty.

Review of low-density parity check codes for 5G new radio

Low-Density Parity-Check Codes (LDPC) as the codes for forwarding error correction have already been adopted into many other wireless standards. Due to the capacity-approaching performance, higher coding gains, and impressive throughput, Low-Density Parity-Check Codes have been adopted in the 5th generation mobile communications (5G). In this paper, LDPC matrix structural features and algorithms for LDPC decoder are presented in use for large blocklength in 5G.The simulations show that algorithm, blocklength, and number of iteration influence the decoding error correction performance.