Decision IC Research Articles

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.

50 Gbit/s low-jitter dynamic decision circuit using Cbc compensation and semi-feed forward techniques

A new low-jitter dynamic decision circuit is designed and fabricated using InP/InGaAs HBTs. Cbc compensation transistors and semi-feed forward loads are adopted to eliminate waveform distortion and residual double trace, respectively. A fabricated decision IC achieves error-free operation and wide eye opening for 50 Gbit/s 231−1 PRBS with 0.68 W power dissipation. Its RMS and peak-to-peak jitter of output data are 0.59 and 4.1 ps, respectively.

45 Gbit/s decision IC module using InAlAs/InGaAs/InPHEMTs

The authors report a 45 Gbit/s decision IC module that uses 0.1 /spl mu/m InAlAs/InGaAs/InP HEMTs. A master-slave D-type flip-flop (D-FF) circuit is adopted as the core D-FF. The module has the fastest operating speed yet reported for master-slave type decision ICs.

40 Gbit/s decision IC using InP/InGaAs composite-collectorheterojunction bipolar transistors

40 Gbit/s error-free operation with a phase margin of 216° has been obtained from a decision IC fabricated using reliable InP/InGaAs composite-collector heterojunction bipolar transistors (CC-HBTs) with a unity current gain cutoff frequency of 116 GHz and a maximum oscillation frequency of 169 GHz. This is the first demonstration of all bipolar transistor decision ICs at such a high bit rate.

20-40-Gbit/s-CLASS GaAs MESFET DIGITAL ICs FOR FUTURE OPTICAL FIBER COMMUNICATIONS SYSTEMS

This paper describes recent advances in high-speed digital IC design technologies based on GaAs MESFETs for future high-speed optical communications systems. We devised new types of a data selector and flip-flops, which are key elements in performing high-speed digital functions (signal multiplexing, decision, demultiplexing, and frequency conversion) in front-end transmitter/receiver systems. Incorporating these circuit design technologies with state-of-the-art 0.12 μm gate-length GaAs MESFET process, we developed a DC-to-44-Gbit/s 2:1 data multiplexer IC, a DC-to 22-Gbit/s static decision IC, and a 20-to-40-Gbit/s dynamic decision IC. The fabricated ICs demonstrated record speed performances for GaAs MESFETs. Although further operating speed margin is still required, the GaAs MESFET is a potential candidate for 20- to 40-Gbit/s class applications.

40 Gbit/s high sensitivity optical receiver withuni-travelling-carrier photodiode acting as decision IC driver

The authors demonstrate a 40 Gbit/s simple optical receiver that uses a uni-travelling-carrier photodiode as a decision IC driver. The photodiode drives the decision circuit directly with 1 Vp-p without any electrical amplifier. Receiver sensitivity of –27.8 dBm was obtained at 40 Gbit/s.

32 Gbit/s super-dynamic decision IC using 0.13 µmGaAs MESFETs with multilayer-interconnection structure

The authors report on a super-dynamic decision IC using 0.13 /spl mu/m gate-length GaAs MESFETs. Using a combination of high-speed circuit and device technologies together with a multilayer interconnection structure, 32 Gbit/s decision operation was achieved.

Low power data decision IC for 20–40 Gbit/sdata links using 0.2 µm AlGaAs/GaAs HEMTs

A decision IC for optical data links at bit rates of 20-40 Gbit/s has been realised by using 0.2 /spl mu/m AlGaAs/GaAs HEMT technology and tested on-wafer at bit rates up to 25 Gbit/s. The IC can be operated with a supply from /spl sim/3.3 to 5.2 V and a DC current of /spl sim/50 mA.

A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Si-analog IC's for 20 Gb/s optical receiver

Two Si-Analog IC's, a preamplifier IC and a decision IC, for a 20 Gb/s optical receiver have been developed using SiGe-base bipolar transistors having a 60 GHz maximum cutoff frequency. The preamplifier employing a dual feedback loop increases the -3 dB bandwidth up to 19 GHz. A decision IC, composed of a gain controllable amplifier with a bias stabilization circuit and D-F/F, operated at up to 20 Gb/s with a 200-mVp-p input sensitivity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

20 Gbit/s AlGaAs/GaAs-HBT 2:1 selector and decision ICs

A 2:1 selector and a decision IC have been fabricated using self-aligned AlGaAs/GaAs HBTs with a 2/μm × 5μm emitter having a cutoff frequency of 62 GHz and a maximum oscillation frequency of 108 GHz. Operation exceeding 20 Gbit/s was demonstrated with these ICs in 2:1 multiplexer and 1:2 demultiplexer experiments.

12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology

Circuit technology that achieves a high-bit-rate decision circuit with high input sensitivity for application to future optical communication systems by using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is reviewed. This technology includes a highly accurate transistor model expressing the overshoot effect and a novel circuit configuration with a wideband preamplifier and an internal buffer. The decision IC operates at up to 12 Gb/s, using AlGaAs/GaAs HBTs with f/sub T/ of 40 GHz. A good sensitivity of 71 mV/sub p-p/ and a wide phase margin of 217 degrees at 11 Gb/s is also achieved under error-free conditions (less than 10/sup -9/ errors).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

400 Mbit/s Optical Regenerator Integrated Circuits

This paper discusses 400 Mbit/s optical regenerator integrated circuits, focusing on their circuit architecture and performance, and describes their application to a 400 Mbit/s optical regenerator. The basic design concepts for high-speed regenerator IC's are discussed and a new integrated circuit architecture based on these design concepts is proposed. The proposed architecture of regenerator IC's is used to fabricate five IC chips (Reshaping IC, Retiming IC, Decision IC, LD driver IC, and dc-to-dc converter IC) using a high-speed bipolar process with transistors having a unity gain bandwidth of 5 GHz. The combination of these IC's can achieve submarine and terrestrial long-haul optical transmission at bit rates up to 450 Mbits/s. These IC's are applied to a 400 Mbit/s IC optical regenerator. Experimental results show that the IC optical regenerator has an optical dynamic range of more than 27 dB without any adjustment and received average optical power required to maintain a 10-11error rate is less than -38 dBm. Experimental results fully satisfy the system requirements, and the feasibility of commercial application is demonstrated.

Integrated Optical Submarine Repeater Circuits Using a High Reliability Process Technology

Repeater IC's for a high-speed optical submarine transmission system are integrated on five monolithic chips using a Si shallow junction bipolar process with 7 GHz f T . To achieve high reliability, a two-level metallization system using Cu-doped Al and Au//Pt/Ti with TiN diffusion barriers is employed. The gain (s 21 ) and bandwidth of the equalizing amplifier IC are 65 dB and 300 MHz, respectively. The timing amplifier IC phase deviation is kept within 10°. The decision IC sensitivity is less than 6 mV. These results fully satisfy performance requirements for repeater IC's.

Integrated optical submarine repeater circuits using a high reliability process technology

Repeater ICs for a high-speed optical submarine transmission system are integrated on five monolithic chips using a Si shallow junction bipolar process with 7 GHz f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> . To achieve high reliability, a two-level metailization system using Cu-doped Al and Au/Pt/Ti with TiN diffusion barriers is employed. The gain (s <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</inf> ) and bandwidth of the equalizing amplifier IC are 65 dB and 300 MHz, respectively. The timing amplifier IC phase deviation is kept within 10°. The decision IC sensitivity is less than 6 mV. These results fully satisfy performance requirements for repeater ICs.