Decision Feedback Equalizer Research Articles

Low complexity nonlinear detection for multiuser hybrid MIMO systems and performance analysis

This paper proposes an analytical framework and a system of distortion-aware receiver structures for single-carrier uplink hybrid beamforming-based multiple-input-multiple-output (MIMO) channels. Proposed single-user processing units cooperate at the base station (BS) in an iterative manner for multi-user symbol detection under hardware impairments. Firstly, in the proposed system, an iterative nonlinear interference cancellation (nIC) based on feedforward neural network (NN) modeling is developed to eliminate the nonlinear distortion effects of power amplifiers (PAs). Furthermore, depending on the fading pattern of the instantaneous channel, it is analytically shown that a large gain may be applied to the distortion signal during the equalization stage, which yields distortion amplification causing a significant decrease in the signal-to-distortion-plus-noise ratio (SDNR). A reduced complexity distortion aware detector, based on a bank of fractionally delayed iterative block decision feedback equalization (IB-DFE) receivers, is introduced to adjust the combiner weights for fractionally delayed IB-DFE outputs so that distortion power is minimized before detection. Consequently, multi-user detection capability is enhanced considerably. Secondly, an asymptotic SDNR analysis is performed. The theoretical analysis, verified via numerical evaluations, clearly shows that distortion amplification limits the achievable SDNR at the BS, and the proposed reduced complexity multi-user receiver architecture improves the BER performance by effectively mitigating this effect.

Adaptive parallel decision deep neural network for high-speed equalization.

The equalization plays a pivotal role in modern high-speed optical wire-line transmission. Taking advantage of the digital signal processing architecture, the deep neural network (DNN) is introduced to realize the feedback-free signaling, which has no processing speed ceiling due to the timing constraint on the feedback path. To save the hardware resource of a DNN equalizer, a parallel decision DNN is proposed in this paper. By replacing the soft-max decision layer with hard decision layer, multi-symbol can be processed within one neural network. The neuron increment during parallelization is only linear with the layer count, rather than the neuron count in the case of duplication. The simulation results show that the optimized new architecture has competitive performance with the traditional 2-tap decision feedback equalizer architecture with 15-tap feed forward equalizer at a 28GBd, or even 56GBd, four-level pulse amplitude modulation signal with 30dB loss. And the training convergency of the proposed equalizer is much faster than its traditional counterpart. An adaptive mechanism of the network parameter based on forward error correction is also studied.

A robust iterative receiver for single carrier underwater acoustic communications under impulsive noise

Achieving reliable underwater acoustic (UWA) communications is challenging due to the rapid changes of UWA channels and presence of impulsive noise. The soft decision feedback equalization (SDFE) has attracted much attention due to its capability of tackling the rapid changes of UWA channels. However, the existing SDFE exhibits error floor and even divergence due to the presence of severe impulsive noise. To overcome this problem, an improved SDFE (ISDFE) is proposed, which incorporates impulsive noise detection, clipping level estimation and damping to handle the impulsive noise. As the performance of the ISDFE also depends on the accuracy of channel estimation (CE), we propose a variable kernel width maximum complex correntropy criterion Kalman filter (VKW-MCCC-KF) algorithm to achieve robust and accurate CE under impulsive noise. With the proposed ISDFE and VKW-MCCC-KF, an iterative receiver for single carrier (SC) UWA mobile communication under impulsive noise is proposed, which incorporates the adaptive broadband Doppler compensation, VKW-MCCC-KF based CE and ISDFE, working in an iterative manner. Experimental results show that, compared with existing receivers, the proposed receiver achieves better performance and robustness to impulsive noise under fast changing UWA channels.

Comparison of post-equalizers for beyond 100-Gb/s/[formula omitted] C-band signal transmission over a 100-km dispersion-uncompensated SSMF

A comprehensive comparison among different post-equalizers with relatively low complexity is studied for C-band 100-km dispersion-uncompensated standard single-mode fiber (SSMF) intensity modulation and direct detection (IM/DD) transmission systems with data rate beyond 100 Gb/s/λ. These representative post-equalizers include feed-forward equalizer (FFE), polynomial-based nonlinear FFE (P-NFFE), absolute-term based nonlinear FFE (AT-NFFE), FFE combined with decision-feedback equalizer (FFE-DFE), polynomial based nonlinear FFE-DFE (P-NLE), absolute-term based nonlinear FFE-DFE (AT-NLE), and their lower-complexity versions of FFE-DFE-WS, P-NLE-WS, and AT-NLE-WS which use weight sharing (WS) to eliminate weight redundancy. We demonstrate 100-Gb/s/λ and 112-Gb/s/λ on-off keying (OOK) transmissions over a 100-km SSMF. For 112-Gb/s transmission, BERs of FFE-DFE(-WS), P-NLE(-WS), and AT-NLE(-WS) can reach 7% hard-decision forward error correction (HD-FEC) limit at 3.8 × 10−3. Under 7% HD-FEC limit, AT-NLE-WS with 32 real-valued multiplications shows similar BER performance as P-NLE and AT-NLE with a small power penalty of < 0.4 dB, but outperforms P-NLE-WS, AT-NLE, and P-NLE in huge complexity reduction of approximately 83.2%, 92.4%, and 92.7%, respectively. Therefore, taking both the BER performance and the operation complexity into account, AT-NLE-WS is the optimal equalizer and is a strong candidate to be applied in low-cost C-band IM/DD interconnections with data rates beyond 100 Gb/s/λ and transmission distance up to 100 km.

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

This article presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) receiver with a Baud-rate clock and data recovery (CDR) suitable for multi-level signaling. By deriving the relation between the vertical eye margin (VEM) and the ratio of main-cursor to pre-cursor, the proposed Baud-rate phase detector (BRPD) adjusts the pre-cursor and finds the lock point with targeted vertical eye opening. Thus, the BRPD offers a unique lock point when used with an adaptive decision feedback equalizer (DFE) where post-cursor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$h_{1}$</tex-math> </inline-formula> is removed. Otherwise, the lock point could drift with the conventional Mueller–Müller phase detector (PD). Furthermore, a summer loading of the DFE reduces the input loading of the DFE by embracing the RZ sampler output instead of the conventional NRZ output, which adds to the delay associated with an RS latch. A prototype chip fabricated in 40-nm CMOS technology consists of an analog front-end (AFE), a phase rotator (PR), a current digital-to-analog converter (DAC), and synthesizable digital logic (SDL), occupying a total active area of 0.24 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . The proposed PAM-4 receiver achieves a bit-error rate (BER) of less than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-11}$</tex-math> </inline-formula> at 48 Gb/s and offers an energy efficiency of 2.42 pJ/b.

PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance

This study presents a wireline pulse amplitude modulation-4 (PAM-4) receiver using the least significant bit (LSB) decoding method that uses the offset of comparators. The proposed LSB decoding method can generate the same output as that of a conventional comparator by effectively adding the desired offset voltage to only one of the differential PAM-4 signals. Because the proposed decoding method replaces a 4-input comparator with a 2-input comparator, it can improve the bit error rate (BER) performance of the LSB by as much as the most significant bit (MSB). The predetermined offset is useful not only for LSB decoding but also for the direct decision feedback equalizer (DFE) operation. The differential amplitude and common-mode voltage (VCM) of the PAM-4 signal vary owing to the direct DFE tap coefficient. The modified comparator can generate an appropriate offset voltage without an adaptation loop or a VCM compensator although the PAM-4 signals are changed depending on the DFE tap coefficient. A prototype is fabricated using 28-nm CMOS technology and tested using a 10.29 dB channel attenuation at 10 GHz. The maximum data rate is 40 Gb/s, and the power efficiency and area of the proposed architecture are 1.58 pJ/bit and 0.039 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , respectively.

Optical amplification-free deep reservoir computing-assisted high-baudrate short-reach communication.

An optical amplification-free deep reservoir computing (RC)-assisted high-baudrate intensity modulation direct detection (IM/DD) system is experimentally demonstrated using a 100G externally modulated laser operated in C-band. We transmit 112 Gbaud 4-level pulse amplitude modulation (PAM4) and 100 Gbaud 6-level PAM (PAM6) signals over a 200-m single-mode fiber (SMF) link without any optical amplification. The decision feedback equalizer (DFE), shallow RC, and deep RC are adopted in the IM/DD system to mitigate impairment and improve transmission performance. Both PAM transmissions over a 200-m SMF with bit error rate (BER) performance below 6.25% overhead hard-decision forward error correction (HD-FEC) threshold are achieved. In addition, the BER of the PAM4 signal is below the KP4-FEC limit after 200-m SMF transmission enabled by the RC schemes. Thanks to the use of a multiple-layer structure, the number of weights in deep RC has been reduced by approximately 50% compared with the shallow RC, whereas the performance is comparable. We believe that the optical amplification-free deep RC-assisted high-baudrate link has a promising application in intra-data center communications.

90-m/560-Mbps underwater wireless optical communication utilizing subband multiple-mode full permutation CAP combined with an SNR-weighted detector and multi-channel DFE.

In this paper, a joint signal processing scheme including a subband multiple-mode full permutation carrierless amplitude phase modulation (SMMP-CAP), signal-to-noise ratio weighted detector (SNR-WD), and multi-channel decision feedback equalizer (MC-DFE) is proposed to mitigate the bandwidth limitation of a high-speed long-reach underwater wireless optical communication (UWOC) system. Referring to the trellis coded modulation (TCM) subset division strategy, 16 quadrature amplitude modulation (QAM) mapping set is divided into four 4-QAM mapping subsets by SMMP-CAP scheme. An SNR-WD and an MC-DFE are employed to enhance the demodulation effect of this system in a fading channel. In a laboratory experiment, the minimal required received optical powers (ROPs) for data rates of 480 Mbps, 600 Mbps, and 720 Mbps, at hard-decision forward error correction (HD-FEC) threshold of 3.80 × 10-3, are -32.7 dBm, -31.3 dBm, and -25.5 dBm, respectively. Moreover, the proposed system successfully achieves a data rate of 560 Mbps in a swimming pool with a transmission distance up to 90 m and a total attenuation measured to be 54.64 dB. To the best of our knowledge, this is the first time to demonstrate a high-speed, long-distance UWOC system by employing an SMMP-CAP scheme.

A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE

In this brief, a 16-Gb/s receiver with a charge-redistribution decision-feedback equalizer (CR DFE) is presented. The proposed CR DFE does not suffer from a voltage headroom issue because it uses charges on the capacitors rather than the current source. Hence, the power consumption is significantly reduced compared with the current-steering DFE. In addition, as the CR DFE tracks the signal and immediately compensates for the inter-symbol interference (ISI), the DFE loop delay is minimized. The equalized output maintains the input common-mode voltage level and signal swing. The CR DFE core fabricated in a 28-nm CMOS technology consumes only 0.38 mA from a 1-V supply at 16 Gb/s and compensates for a 12.5-dB ISI channel. An FoM of 0.0019 pJ/bit/dB was achieved, which is significantly better than the state-of-the-art technologies.

Optical Amplification-Free High Baudrate Links for Intra-Data Center Communications

The enormous traffic growth sets a stringent requirement to upgrade short-reach optical links to 1.6 TbE capacity in an economically viable way. The power consumption and latency in these links should be as low as possible, especially for high-speed computing. This is possible to achieve using high baudrate on-off keying links thanks to a better noise tolerance and a relaxed requirement on linearity for electronics and photonics. In this regard, we demonstrate a 200 Gbaud on-off keying link without any optical amplification using an externally modulated laser with 3.3 dBm of modulated output power operating at 1541.25 nm wavelength. We achieve transmission over 200 meters of single-mode fiber with performance below 6.25% overhead hard-decision forward error correction threshold for each baudrate and all selection of modulation formats. We also show 108 Gbaud on-off keying link with superior performance without decision feedback equalizer up to 400 meters of single-mode fiber. In addition, we benchmark the short-reach optical link with 112 Gbaud four-level pulse amplitude modulation and 100 Gbaud six-level pulse amplitude modulation. For 108 Gbaud on-off keying and 112 Gbaud four-level pulse amplitude modulation, we can achieve an even lower bit error rate.

Improved Weighted Volterra DFE for C-Band 100-Gbit/s PAM-4 Transmission Over 60-km SSMF

To cope with the nonlinear distortions and the chromatic dispersion (CD) induced power fading in double-side band (DSB) intensity modulation and direct detection (IM/DD) transmission systems, high-performance Volterra decision-feedback equalizers (VDFEs) are widely applied. However, similar as linear DFE, the VDFEs suffer from error propagation in the case of wrong decisions. In this letter, to reduce the error propagation probability of VDFEs, we propose and experimentally demonstrate a diagonally-pruned improved weighted VDFE (DP-IWVDFE) in a C-band 4-level pulse amplitude modulation (PAM-4) transmission system. By replacing the hard-decision output by the soft-decision feedback symbol based on a compressed sigmoid nonlinear function in DP-IWVDFE, the error propagation probability can be significantly reduced, which lowers the bit error ratio (BER) by a factor of around two as compared to the DP-VDFE. Besides, 100-Gbit/s PAM-4 transmission over 60-km standard single-mode fiber (SSMF) using DP-IWVDFE is realized with the achieved BER below 3.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{-3}$ </tex-math></inline-formula> , achieving around 3.8-dB, 1.5-dB, and 1-dB improvements of the receiver sensitivity over the polynomial DFE (PDFE), improved weighted PDFE (IWPDFE), and DP-VDFE, respectively.

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

This work proposes a RX front-end structure, which is used for channel equalization of 25Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005mm2 designed in 65nm CMOS, the power consumption of which is 96mW under 1.2V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35dB at 12.5GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171mV and 0.61UI at the BER of 10-12, respectively.

A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.

Long Short-Term Memory Neural Equalizer

A trainable neural equalizer based on Long Short-Term Memory (LSTM) neural network architecture is proposed in this paper to recover the channel output signal. The current widely used solution for the transmission line signal recovery is generally realized through a decision feedback equalizer (DFE) or forward-feedback equalizer (FFE-DFE) combination. The novel learning-based equalizer is suitable for highly non-linear signal restoration thanks to its recurrent design. The effectiveness of the LSTM equalizer (LSTME) is shown through an advance design system (ADS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^@$</tex-math></inline-formula> ) simulation channel signal equalization task including a quantitative and qualitative comparison with an FFE-DFE combination. The LSTM neural network shows good equalization results compared to that of the FFE-DFE combination. The advantage of a trainable LSTM equalizer lies in its ability to learn its parameters in a flexible manner and to tackle complex scenarios without any hardware modification. This can reduce the equalizer implantation cost for variant transmission channels and bring additional portability in practical applications.

A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces

This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the present data with previous data. The RX was implemented as half-rate architecture to halve the clock frequency and facilitate the S&H operation. Moreover, the proposed decision feedback equalizer (DFE) is suitable for SR RX and improves the reliability of RX by eliminating inter-symbol interference (ISI). The prototype RX, fabricated using 28-nm CMOS technology, occupies a 0.0016 mm2 active area. The measurement result of the proposed RX achieves a bit-error-rate (BER) under 10−12 with a 15-Gb/s data rate in a 17-inch PCB FR4 channel. The RX consumes 13.56 mW of power and has a power efficiency of 0.90 pJ/bit.

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front-end (AFE) that incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer (DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO). The RX was characterized for medium-to-long reach channels (20.6-, 27-, 31.4-, and 38-dB insertion loss at Nyquist) with a corresponding pre-forward error correction (FEC) bit error rates of 1.9E-11, 5.2E-10, 1.2E-8, and 6E-7, respectively. The analog power consumption of the RX is 1.41 pJ/b.

Lake Experimentation of in-Band Full-Duplex Underwater Acoustic Communications With a Receiving Array

In-band full-duplex (IBFD) communications is a promising technique to achieve spectral-efficient communication in the underwater environment. To achieve IBFD underwater communications, suppression of self-interference (SI) is a prerequisite. In this paper, SI suppression using physical separation and digital SI cancellation is investigated under different transmitter-receiver geometries. An iterative IBFD receiver combining joint channel estimation, SI cancellation, and multichannel decision feedback equalizer is developed. Due to the potential deterioration of the channel estimation accuracy, a digital SI cancellation control mechanism is used to regulate the suppression process. The feasibility of coherent IBFD underwater acoustic communications was tested in a lake environment. The two SI suppression methods, the SI cancellation control mechanism, and the receiver performance were evaluated using the experimental measurements. A bit error rate (BER) in the order of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-2}$ </tex-math></inline-formula> was achieved at the range of 80 m for IBFD communications.

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter. Generally multipliers, adders and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this, multiplier less architecture are needed in FIR filter. So Distributed Arithmetic architecture place a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of FIR filter and at same time the area will be decreased. The proposed design is synthesized and implemented in Synapsis design compiler tool. The area, power delay product, frequency, area delay product and power of the proposed design are calculated. When we observe the synthesis results, the proposed design has 15% high frequency rate when compare with the existing design. Also the proposed design is more useful in signal processing applications like decision feed-back equalizer.

Demonstration of 200 Gbps PAM-4 transmission in a limited-bandwidth system using a two-tap THP with nonlinearity compensator

In this paper, we have proposed a digital signal processing (DSP) method for a 200 Gbps pulse-amplitude modulation level-4 (PAM-4) transmission in a bandwidth-limited system. To mitigate inter-symbol interferences (ISI) in the system and reduce the propagation of errors in the receiver, the Tomlinson-Harashima precoding (THP) technique was applied to the transmitter. For simplicity, the number of THP taps was limited to two (i.e., one coefficient to be optimized); the residual ISI resulting from the short tap was compensated for with a decision feedback equalizer (DFE). The performance of the proposed DSP was analyzed via experiments and simulations. Compared to conventional DSP techniques (such as DFE and the maximum likelihood sequence estimation (MLSE) without THP), the proposed DSP performs better within the limited-bandwidth region. As a result, the soft-decision forward error correction (SD-FEC) threshold (of 2 × 10−2) was satisfied even when the bandwidth fell to below 35% of the baud rate. To enhance this performance, post-filter and MLSE were additionally applied, after which its performance was investigated. In addition, the nonlinear characteristics of the components were alleviated by applying a pre-distortion technique to the THP using look-up tables; this further enhanced performance, lowering the SD-FEC threshold’s bandwidth to 32% of the baud rate.

Effects of acoustic nonlinearity on communication performance in soft tissues.

Acoustic communication has been gaining traction as an alternative communication method in nontraditional media, such as underwater or through tissue. Acoustic propagation is known to be a nonlinear phenomenon; nonlinear propagation of acoustic waves in soft tissues at biomedical frequencies and intensities has been widely demonstrated. However, the effects of acoustic nonlinearity on communication performance in biological tissues have not yet been examined. In this work, nonlinear propagation of a communication signal in soft tissues is analyzed. The relationship between communication parameters (signal amplitude, bandwidth, and center frequency) and nonlinear distortion of the communication signal propagating in soft tissues with different acoustic properties is investigated. Simulated experiments revealed that, unlike linear channels, bit error rates increase as signal amplitude and bandwidth increase. Linear and decision feedback equalizers fail to address the increased error rates. When tissue properties and transmission parameters can be estimated, receivers based on maximum likelihood sequence estimation approach the performance of an ideal receiver in an ideal additive white Gaussian noise channel.