Decimal Operations Research Articles

Architectures for multiple constant decimal multiplication

Due to the increasing demand for decimal calculations in the business, financial and economic world, decimal arithmetic circuits have been much considered by system designers. This is mainly because, these applications heavily depend on decimal arithmetic since the results must match exactly those obtained by human calculations. While decimal multiplication is one of the most frequent and complex-to-implement decimal operations, the special case of constant decimal multiplication is widely used in the economic and financial applications. In this paper, we propose two ideas, named “Constant Decimal TCSD” (CDT) and “Constant Decimal DDDS” (CDD), and their hardware implementations for realizing multiple constant decimal multiplication. In the CDT and CDD architectures, the partial products are generated using a set of positive multiplicand multiples coded in2′s complement signed-digit format (TCSD) and binary coded decimal (BCD), respectively. We also present two new (3:1) compressors to reduce the number of partial products in both designs, one based on a new Double Decimal Digit Set (DDDS), which is not only self-complementing but also its redundancy, allows carry-free addition. Finally, a redundant to non-redundant converter recodes the TCSD and DDDS product to BCD in the first and second schemes, respectively. Hardware synthesis evaluation shows that compared to the most recent 16 × 16 decimal multipliers, delay, area, power consumption and PDP of the proposed multiple constant multipliers improve up to 57%, 89%, 93% and 97%, respectively.

Moving shadow detection based on stationary wavelet transform

Many surveillance and forensic applications face problems in identifying shadows and their removal. The moving shadow points overlap with the moving objects in a video sequence leading to misclassification of the exact object. This article presents a novel method for identifying and removing moving shadows using stationary wavelet transform (SWT) based on a threshold determined by wavelet coefficients. The multi-resolution property of the stationary wavelet transform leads to the decomposition of the frames into four different bands without the loss of spatial information. The conventional discrete wavelet transform (DWT), which has the same property, suffers from the problem of shift invariance due to the decimation operation leading to a shift in the original signal during reconstruction. Since SWT does not have the decimation operation, the problem of shift invariance is solved which makes it feasible for change detection, pattern recognition and feature extraction and retrieves the original signal without the loss of phase information also. For detection and removal of shadow, a new threshold in the form of a variant statistical parameter—“skewness”—is proposed. The value of threshold is determined through the wavelet coefficients without the requirement of any supervised learning or manual calibration. Normally, the statistical parameters like mean, variance and standard deviation does not show much variation in complex environments. Skewness shows a unique variation between the shadow and non-shadow pixels in various environments than the previously used thresholds—standard deviation and relative standard deviation. The experimental results prove that the proposed method works better than other state-of-art-methods.

Design and Implementation of Floating Point Unit using 15 nm FIFET

Objectives: To design a 32-bit IEEE 754 floating point standard based MAC unit using 15 nm FinFET. In MAC unit given data is multiplied and accumulated in a register which are processed separately as exponent and mantissa but there are some issues regarding area power and timing, compromising these constraints is bit difficult. Methods: The proposed architecture of floating point MAC unit is majorly divided into multiplier and accumulator components in these blocks the sub blocks are designed with Han-Carlson adder, Vedic multiplier, barrel shifter and comparator. Findings: The previous work was done in Hardware Description Language (HDL) in which the design will map to CMOS or pass transistor components after synthesis so designing of each component with transistors of 15 nm FINFET becomes vital. The entire design is carried out in cadence virtuoso and layout editor for timing, area and power. The performance can be increased if the computations are performed with less number of transistors. However, the decimal operations have been limited due to the increase in cost and complexity of hardware components. DFP arithmetic is used for the complex computations, it consumes more power because of the area it occupied when implemented in hardware. Improvements/Applications: Because of battery driven property low power with high performance are given major importance.

High Performance Multi-Operand Adder for Medical Images

AbstractThe Internet of Things (IoT) gives a new path for future Internet through which it had boosted the growth in number of devices ranging from home automation to medical devices. Security in IoT is a research topic, which involves security for low memory footprint devices. Hence light weighted cryptographic algorithms plays a major role in providing data integrity for IoT devices. The term light weightiness begins from gate level to system level. Multi-operand addition, which is widely used in block ciphers and hash functions. This work presents different approaches for realization of highly efficient multi-operand addition for medical IoT field devices. The use of conventional adders in the multipliers for summation of the intermediate results leads to area and delay overhead. Multi-operand addition and compressor trees can be used more efficiently for decimal operations, which will reduce the delay without much overhead in area. The proposed approach is experimented with different multipliers for i...

A Radical Approach to Computation with Real Numbers

If we are willing to give up compatibility with IEEE 754 floats and design a number format with goals appropriate for 2016, we can achieve several goals simultaneously: Extremely high energy efficiency and information-per-bit, no penalty for decimal operations instead of binary, rigorous bounds on answers without the overly pessimistic bounds produced by interval methods, and unprecedented high speed up to some precision. This approach extends the ideas of unum arithmetic introduced two years ago by breaking completely from the IEEE float-type format, resulting in fixed bit size values, fixed execution time, no exception values or “gradual underflow” issues, no wasted bit patterns, and no redundant representations (like “negative zero”). As an example of the power of this format, a difficult 12-dimensional nonlinear robotic kinematics problem that has defied solvers to date is quickly solvable with absolute bounds. Also unlike interval methods, it becomes possible to operate on arbitrary disconnected subsets of the real number line with the same speed as operating on a simple bound.

Fast Radix-10 Multiplication Using Redundant BCD Codes

We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speedup its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition, new techniques are developed to reduce significantly the latency and area of previous representative high-performance implementations. Partial products are generated in parallel using a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-5, 5], and a set of positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) coded in XS-3. This encoding has several advantages. First, it is a self-complementing code, so that a negative multiplicand multiple can be obtained by just inverting the bits of the corresponding positive one. Also, the available redundancy allows a fast and simple generation of multiplicand multiples in a carry-free way. Finally, the partial products can be recoded to the ODDS representation by just adding a constant factor into the partial product reduction tree. Since the ODDS uses a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, such as binary carry-save adders and compressor trees, can be adapted efficiently to perform decimal operations. To show the advantages of our architecture, we have synthesized a RTL model for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$16\times 16$</tex-math></inline-formula> -digit and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$34\times 34$</tex-math></inline-formula> -digit multiplications and performed a comparative survey of the previous most representative designs. We show that the proposed decimal multiplier has an area improvement roughly in the range 20-35 percent for similar target delays with respect to the fastest implementation.

A two-channel perfect reconstruction filter bank associated with the linear canonical transform

Sampling rate conversion is one of the most important concepts in modern signal processing community; it can be realised by interpolation and decimation operations. Based on the scaling operation and following the idea of the classical results, this paper investigate the sampling rate conversion associate with the discrete time linear canonical transform (DTLCT). First, we derive a new structure of sampling rate conversion for any rational or irrational factors in the linear canonical transform domain, then a two-channel nonuniform perfect reconstruction filter bank in the linear canonical transform domain is proposed based on the sampling rate conversion; the simulations are also performed to verify the derived results.

Decimal SRT Square Root: Algorithm and Architecture

Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic of research in recent decades. Besides the four basic operations, the square root can be implemented as an instruction directly in the hardware, which improves the performance of the decimal floating-point unit in the processors. Hardware implementation of decimal square rooters is usually done using either functional or digit-recurrence algorithms. Functional algorithms, entailing multiplication per iteration, seem inadequate to use for decimal square roots, given the high cost of decimal multipliers. On the other hand, digit-recurrence square root algorithms, particularly SRT (this method is named after its creators, Sweeney, Robertson, and Tocher) algorithms, are simple and well suited for decimal arithmetic. This paper, with the intention of reducing the latency of the decimal square root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square root. The proposed fixed-point square root design requires n+3 cycles to compute an n-digit root; the synthesis results show an area cost of about 31K NAND2 and a cycle time of 40 FO4. These results reveal the 14 % speed advantage of the proposed decimal square root architecture over the fastest previous work (which uses a functional algorithm) with about a quarter of the area.

International Judging System of Figure Skating: A Middle Grades Activity on Decimal Operations

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On Basic Financial Decimal Operations on Binary Machines

Financial transactions are specified in decimal arithmetic. Until the introduction of IEEE 754-2008, specialized software/hardware routines were used to perform these transactions but it incurred a penalty on performance. In this paper, we show that if binary arithmetic is used to emulate decimal operations, then arbitrary error sequences can be generated by carefully chosen sequences of transactions which can lead to monotonically increasing/decreasing capitalization errors. In addition, we describe methods for correctly performing basic decimal operations, such as addition, subtraction, multiplication, and division, on binary machines, which are not conformant with IEEE 754-2008 decimal floating point standard (ISO/IEC/IEEE 60559:2011), at high speed.

Reducing frequency-domain artifacts of binary image due to coarse sampling by repeated interpolation and smoothing of Radon projections

We develop a method to calculate 2D spectrum of a binary image with better quality than that obtained via direct 2D-FFT. With FFT, jagged edges of objects due to coarse sampling introduce artifacts into the frequency domain, especially in the high-frequency area. With the proposed method, Radon projections of the binary image along lines at different viewing angles are calculated. Each projection is extended by interpolation, then smoothed and decimated. The interpolation–smoothing–decimation operation is repeated several times to reduce ruggedness and improve quality of the Radon projections considerably. One-dimensional FFT of each refined Radon projection is calculated, resulting in a set of frequency-domain samples distributed on a polar coordinate system. These samples are interpolated onto a Cartesian grid to give the required 2D spectrum of the sampled binary image. Numerical computations on several objects show that the method can provide significant improvement to the spectrum as compared with direct 2D-FFT.

Image misalignment caused by decimation in image fusion evaluation

In the evaluation of image fusion methods, spatially degraded multispectral (MS) and panchromatic (PAN) images are frequently employed as test data sets. The degradation is implemented using either averaging or a combination of low-pass filtering and decimation. However, the decimation operation causes the degraded MS and PAN images to be slightly misaligned with each other and with the original MS image, which acts as the reference image in the fusion evaluation. In this study, two image fusion methods based on decimated and undecimated multiresolution analysis techniques were evaluated on three popular types of test data sets consisting of spatially degraded IKONOS MS and PAN images. In the experiment, image misalignments caused by decimation significantly influenced the quality of fused images and resulted in untrustworthy performances of the image fusion methods being evaluated. It was demonstrated that unlike aligned MS and PAN images in actual image fusion, misaligned MS and PAN images in test data sets are inappropriate for image fusion evaluation.

Finite difference time domain calculation of three-dimensional phononic band structures using a postprocessing method based on the filter diagonalization

If the band structure of a three-dimensional (3D) phononic crystal (PNC) is calculated by using the finite difference time domain (FDTD) method combined with the fast Fourier transform (FFT)-based postprocessing method, good results can only be ensured by a sufficiently large number of FDTD iterations. On a common computer platform, the total computation time will be very long. To overcome this difficulty, an excellent harmonic inversion algorithm called the filter diagonalization method (FDM) can be used in the postprocessing to reduce the number of FDTD iterations. However, the low efficiency of the FDM, which occurs when a relatively long time series is given, does not necessarily ensure an effective reduction of the total computation time. In this paper, a postprocessing method based on the FDM is proposed. The main procedure of the method is designed considering the aim to make the time spent on the method itself far less than the corresponding time spent on the FDTD iterations. To this end, the FDTD time series is preprocessed to be shortened significantly before the FDM frequency extraction. The preprocessing procedure is performed with the filter and decimation operations, which are widely used in narrow-band signal processing. Numerical results for a typical 3D solid PNC system show that the proposed postprocessing method can be used to effectively reduce the total computation time of the FDTD calculation of 3D phononic band structures.

A Propagation Analysis of Residual Distributions in Pipeline ADCs

This paper presents a propagation analysis of residual distributions in pipeline ADCs. It relies on the observation that the Frobenius-Perron operator which maps the input probability density of a pipeline stage into its output distribution admits a simple representation in the Fourier domain. It performs a decimation operation followed by a sign modulation operation on the Fourier coefficients of the input density. This representation is used to analyze the convergence of residual distributions to a uniform distribution as more stages are traversed. The analysis can also be used to show that quantization residuals become asymptotically independent. For quantization stages with redundant bits it is also shown that the span of the uniform distribution of quantization residuals need not coincide with the full ADC dynamic range.

Denjoy–Wolff theorems, Hilbert metric nonexpansive maps and reproduction–decimation operators

Let K be a closed cone with nonempty interior in a Banach space X. Suppose that f : int K → int K is order-preserving and homogeneous of degree one. Let q : K → [ 0 , ∞ ) be a continuous, homogeneous of degree one map such that q ( x ) > 0 for all x ∈ K ∖ { 0 } . Let T ( x ) = f ( x ) / q ( f ( x ) ) . We give conditions on the cone K and the map f which imply that there is a convex subset of ∂ K which contains the omega limit set ω ( x ; T ) for every x ∈ int K . We show that these conditions are satisfied by reproduction–decimation operators. We also prove that ω ( x ; T ) ⊂ ∂ K for a class of operator-valued means.

Embedding Probabilities for the Alternating Step Generator

The edit distance correlation attack on the well- known alternating step generator for stream cipher applications was proposed by Golic and Menicocci. The attack can be successful only if the probability of the zero edit distance, the so-called embedding probability, conditioned on a given segment of the output sequence, decreases with the segment length, and if the decrease is exponential, then the required segment length is linear in the total length of the two linear feedback shift registers involved. The exponential decrease for the maximal value of the embedding probability, regarded as a function of the output segment, was estimated experimentally by Golic and Menicocci. In this paper, by using the connection with the interleaving and decimation operations, the embedding probability is analyzed theoretically. Exponentially small upper bounds on the maximal embedding probability are thus derived. An exact expression for the minimal embedding probability is also determined

Under-sampled Weyl–Heisenberg expansions via orthogonal projections in Zak space

An algorithm is presented which orthogonally projects signals into integer under-sampled Weyl–Heisenberg subspaces. The algorithm operates by periodization–decimation operations in Zak space, and can be viewed as direct Zak space extension of classical signal space procedures underlying orthogonal projections of Fourier expansions, the basis of divide and conquer fast Fourier transform algorithms. The language of groups is used, which highlights the duality between time and frequency spaces and facilitates sampling rate conversion. Results of numerical experiments are included, suggesting that the algorithm can be used for arrival time estimation of a partially known signal.

Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures

We perform a thorough data dependence and localization analysis for the discrete wavelet transform algorithm and then use it to synthesize distributed memory and control architectures for its parallel computation. The discrete wavelet transform (DWT) is characterized by a nonuniform data dependence structure owing to the decimation operation it is neither a uniform recurrence equation (URE) nor an affine recurrence equation (ARE) and consequently cannot be transformed directly using linear space-time mapping methods into efficient array architectures. Our approach is to apply first appropriate nonlinear transformations operating on the algorithm's index space, leading to a new DWT formulation on which application of linear space-time mapping can become effective. The first transformation of the algorithm achieves regularization of interoctave dependencies but alone does not lead to efficient array solutions after the mapping due to limitations associated with transforming the three-dimensional (3-D) algorithm onto one-dimensional (1-D) arrays, which is also known as multiprojection. The second transformation is introduced to remove the need for multiprojection by formulating the regularized DWT algorithm in a two-dimensional (2-D) index space. Using this DWT formulation, we have synthesized two VLSI-amenable linear arrays of LPEs computing a 6-octave DWT decomposition with latencies of M and 2M-1, respectively, where L is the wavelet filter length, and M is the number of samples in the data sequence. The arrays are modular, regular, use simple control, and can be easily extended to larger L and J. The latency of both arrays is independent of the highest octave J, and the efficiency is nearly 100% for any M with one design achieving the lowest possible latency of M.

Research into Practice: Place Value as the Key to Teaching Decimal Operations

Some years ago I examined several middle school students' understanding of numbers (Threadgill-Sowder 1984). The answers that students gave me during that study showed me that their understanding, developed largely through experiences in the elementary grades, was fuzzy and led me to undertake a decade of research on children's number sense in the elementary and middle school grades. I will set the stage for this article by sharing two of the questions I gave the students during that study and some of the responses I received.

Novel multirate processing of beamspace noise eigenvectors

A novel implementation of Root-MUSIC is introduced based on the observation that the MUSIC null spectrum created with a beamspace noise eigenvector is bandpass exhibiting nulls at the locations of in-band sources. Thus, after telescoping to element space and modulating to broadside, the telescoped noise eigenvector may be decimated yielding a small order polynominal with the separation between signal roots increased by the decimation factor. Depending on the out-of-band response of the beamformers, the telescoped noise eigenvector may be passed through a lowpass filter prior to decimation to preserve in-band source nulls. A low cost algorithm is realized by invoking linearity and performing the modulation, filtering, and decimation operations a priori on the beamformers yielding a simple transformation to be applied to the beamspace noise eigenvectors. >