Decimation In Time Research Articles

Real-valued decimation-in-time and decimation-in-frequency algorithms

The decimation-in-time (DIT) and the decimation-in-frequency (DIF) algorithms are the typical forms of the fast Fourier transform (FFT) algorithm. Many hardware and software implementations are based on these algorithms. One class of fast algorithms for computing the discrete Fourier transform (DFT) is based on a recursive factorization of the polynomial 1-z/sup N/. This paper introduces a simple recursive factorization of 1-z/sup N/ over the real numbers and a mathematical framework that generalizes the form of the DFT. Using the recursive factorization, efficient algorithms are derived to compute the DFT and the cyclic convolution of sequences of length with a power of two. Real-valued DIT and real-valued DIF algorithms are developed so that the accumulated FFT technologies can be fully utilized for real sequences. Introducing a real-valued butterfly, the algorithmic structures of the DIT and the DIF algorithms are shown to be equally applicable for the real-valued algorithms by systematic modifications. The computational complexity is fairly comparable with other available fast algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New radix-3 and −6 decimation-in-frequency fast Hartley transform algorithms

Fast algorithms of a transform, like fast Fourier transform (FFT) algorithms, are based on different decomposition techniques. It is shown that these decomposition techniques can also be applied to the computation of the discrete Hartley transform (DHT) for a real-valued sequence. Recently, an efficient decomposition technique for radix-3 decimation-in-time (DIT) FFT and fast Hartley transform (FHT) algorithms has been demonstrated. Such a decomposition technique is implemented for radix-3 and -6 decimation-in-frequency (DIF) FHT algorithms and found to improve the operation count. Efficiency in these algorithms is derived by pairing the rotating factors with an appropriate reordering of the input sequence. From the results, it is seen that the radix-3 and -6 FHT algorithms presented are comparable to the split-radix FHT algorithm in terms of their operation count and will be more efficient when the sequence length is closer to an integer power of the corresponding radix.

Application-specific architecture for fast transforms based on the successive doubling method

The successive doubling method is an efficient procedure for the design of fast algorithms for orthogonal transforms of length N=r/sup n/, where the radix r is a power of 2. A partitioned systolic architecture is presented for the two standard radix successive doubling algorithms: decimation in time (DIT) and decimation in frequency (DIF). The index space of the data is projected onto the index space associated with a column of processors, interconnected using a perfect unshuffle (DIT) or shuffle (DIF) interconnection network, defined by permutations of the order log/sub 2/r. The result is a partitioned systolic array with Q processors (Q=r/sup i/, 0<or=i<n), which extracts the maximum spatial and temporal parallelism achieved by the successive doubling algorithm and can be integrated in VLSI and WSI technologies.<<ETX>>

Direct methods for computing discrete sinusoidal transforms

According to Wang, there are four different types of DCT (discrete cosine transform) and DST (discrete sine transform) and the computation of these sinusoidal transforms can be reduced to the computation of the type-IV DCT. As the algorithms involve different sizes of transforms at different stages they are not so regular in structure. Lee has developed a fast cosine transform (FCT) algorithm for DCT-III similar to the decimation-in-time (DIT) Cooley–Tukey fast Fourier transform (FFT) with a regular structure. A disadvantage of this algorithm is that it involves the division of the trigonometric coefficients and may be numerically unstable. Recently, Hou has developed an algorithm for DCT-II which is similar to a decimation-in-frequency (DIF) algorithm and is numerically stable. However, an index mapping is needed to transform the DCT to a phase-modulated discrete Fourier transform (DFT), which may not be performed in-place. In the paper, a variant of Hou&apos;s algorithm is presented which is both in-place and numerically stable. The method is then generalised to compute the entire class of discrete sinusoidal transforms. By making use of the DIT and DIF concepts and the orthogonal properties of the DCTs, it is shown that simple algebraic formulations of these algorithms can readily be obtained. The resulting algorithms are regular in structure and are more stable than and have fewer arithmetic operations than similar algorithms proposed by Yip and Rao. By means of the Kronecker matrix product representation, the 1-D algorithms introduced in the paper can readily be generalised to compute transforms of higher dimensions. These algorithms, which can be viewed as the vector-radix generalisation of the present algorithms, share the in-place and regular structure of their 1-D counterparts.

Implementing fast Fourier transforms using the Am29500 family

The paper discusses the implementation of fast Fourier transform (FFT) algorithms using members of the Am29500 family of microprocessors and peripherals. First the suitability of the Am29500 family for signal processing applications is discussed. The architectural requirements of FFT processors are then outlined. A parallel processing architecture using pipelining is developed and the microprogramming of the system is described. Timing and implementation details, together with some practical test results, are given. The paper concentrates mainly on radix-2 decimation-in-time (DIT) FFT computations, but the architecture described can be applied to variable-radix processors running DIT or DIF (decimation-in-frequency) algorithms.

Fast decimation-in-time algorithms for a family of discrete sine and cosine transforms

Fast decimation-in-time (DIT) algorithms for the various discrete cosine transforms (DCT) and discrete sine transforms (DST) are systematically developed, based on a radix-2 factorization of the transformation matrix. The results indicate these to be attractive alternatives to existing algorithms in terms of computational complexity and structural simplicity.

Error analysis of Good-Winograd algorithm assuming correlated truncation errors

This paper investigates the error performance of the Good-Winograd algorithm (GWA) when implemented in fixed-point mode using sign magnitude or 1's complement arithmetic. Unlike the previous analysis, the present study assumes the noise sources (particularly the truncation errors due to complex scaling) to be correlated both inside and between stages. Expressions for output noise-to-signal ratio (NSR), taking the effect of the correlation between truncation errors in the same path of signal flow, are derived for minimum error ordering of the basic modules. The error predicted by the correlated model (present investigation) is approximately 170 percent of the corresponding value predicted by the uncorrelated model of Patterson and McClellan. On comparison of the results of both the models with the experimental findings, it is, in general, observed that the correlated model predicts results much closer to the corresponding experimental value. Furthermore, the GWA introduces errors almost identical to the correlated model of decimation-in-time (DIT) FFT and hence, with an equal number of data bits can maintain a similar degree of accuracy.

FFT algorithm for both input and output pruning

When an input data sequence has a large number of zeros and the number of output samples required to be computed is small, significant time saving can be achieved by a judicious combination of the pruning algorithms for decimation-in-time (DIT) and decimation-in-frequency (DIF). It is shown that the complementary structure of the DIT and the DIF formulations makes possible the application of the pruning algorithms simultaneously at the input, as well as at the output, for either of the formulations. For a given number of input and output points, a choice between the two formulations can be made based on the amount of time saved in each. Also, a simple assembly language modification is shown by which the bit reversal is made significantly faster.