Debug Data Research Articles

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug

Post-silicon debug has become important with the increased complexity of circuit designs. However, the increase in debug resource costs owing to improved observability has posed a major challenge. To overcome this challenge, this study proposes on-chip error detection that reuses built-in self-repair (BISR). The proposed method utilizes the components of BISR as storages of golden signatures and comparators for error detection. Also, it detects error-suspect cycles more precisely by using parent and child multiple-input signature registers (MISRs). In addition, it provides selective capture and store methods that selectively capture error-suspect debug data in buffers and store them in the DRAM, respectively. The experimental results of various debug cases demonstrate that the proposed method significantly reduces the buffer size, DRAM usage, and debug time compared to previous methods.

An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment

Post-silicon validation is a major challenge due to finite controllability and observability of actual silicon and makes debug a complex task. The trace signals routed from CPUs and other sources are translated by sampling unit to time-stamped trace messages and stored in trace buffer. Time stamp generated is not the exact time at which event has occurred. Hence, trace data read from trace buffer in post-silicon environment is not accurate from debug perspective. This is corrected by finding the variable delay along with various paths observed between two viewpoints, one being the source at which the event occurs and the other being the destination where the event gets recorded. One method to achieve time accurate debug data is by correlating the time at which data transaction event occurs at the signal with the time at which the trace data for that particular transaction event gets time-stamped. The major advantage is the successful reconstruction of pre-silicon environment for that particular post-silicon environment and enabling data to be viewed on the fly.

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug

Silicon debugging is carried out in multiple sessions which are characterized by run-and-halt intervals. One of the important criteria for the success of this method is that the debugging infrastructure should capture only the erroneous data which can add important insights to the debugging process. However, identification of such suspect clock cycles is not a trivial exercise and requires an systematic approach. We propose a debugging architecture for enhancing the multisession procedure using the technique of on-chip debug data compression. The first session assists in identifying those erroneous clock cycles, and the useful debug data are collected in the second session with the help of markers called tag bits. At the cost of a minimal increase in area overhead, the proposed architecture achieves finer temporal visibility expansion because of the debug data collection in a segregated manner. During the offline analysis of the collected debug data, error localization can be achieved to a finer resolution. We evaluate our methodology on several designs for different kinds of error configurations. Experimental results show that the proposed methodology can achieve better on-chip storage utilization and the expansion in the temporal observation window compared to similar techniques in the literature.

Searching for Bugs Using Probabilistic Suspect Implications

Due to the excessive cost associated with manual RTL design debugging, automated tools are often employed to identify a set of suspect bug locations. To further accelerate the process, one observes that the anytime behavior of these tools allows partial results to be analyzed before the suspect search is complete. Thus, it is preferable for the tool to maximize the number of suspects that are found in the early stages of its search. Toward this end, this article proposes a new SAT-based debugging algorithm which predicts where solutions are most likely to be found and prioritize examining these locations. Two techniques are proposed to predict solution locations by learning from historical debug data. The first technique does so using belief propagation on a probabilistic graph, while the second trains a neural network to classify candidate suspects as solutions or nonsolutions. Intensive empirical evaluation demonstrates that these techniques can predict suspect sets with accuracies of 81% and 87%, respectively, but the second method requires more training data and careful hyperparameter tuning in order to do so. Furthermore, when guided by these suspect prediction models, the proposed debugging algorithm finds an average of 83% more suspects within a given amount of time.

A debug scheme to improve the error identification in post-silicon validation

While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

Post-silicon platform for the functional diagnosis and debug of networks-on-chip

The increasing number of units in today's systems-on-chip and multicore processors has led to complex intra-chip communication solutions. Specifically, Networks-on-Chip (NoCs) have emerged as a favorable fabric to provide high bandwidth and low latency in connecting many units in a same chip. To achieve these goals, the NoC often includes complex components and advanced features, leading to the development of large and highly complex interconnect subsystems. One of the biggest challenges in these designs is to ensure the correct functionality of this communication infrastructure. To support this goal, an increasing fraction of the validation effort has shifted to post-silicon validation, because it permits exercising network activities that are too complex to be validated in pre-silicon. However, post-silicon validation is hindered by the lack of observability of the network's internal operations and thus, diagnosing functional errors during this phase is very difficult. In this work, we propose a post-silicon validation platform that improves observability of network operations by taking periodic snapshots of the traffic traversing the network. Each node's local cache is configured to temporarily store the snapshot logs in a designated area reserved for post-silicon validation and relinquished after product release. Each snapshot log is analyzed locally by a software algorithm running on its corresponding core, in order to detect functional errors. Upon error detection, all snapshot logs are aggregated at a central location to extract additional debug data, including an overview of network traffic surrounding the error event, as well as a partial reconstruction of the routes followed by packets in flight at the time. In our experiments, we found that this approach allows us to detect several types of functional errors, as well as observe, on average, over 50% of the network's traffic and reconstruct at least half of each of their routes through the network.

Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug

This paper presents a novel technique for extending the capacity of trace buffers when capturing debug data during post-silicon debug. It exploits the fact that is it not necessary to capture error-free data in the trace buffer since that information can be obtained from simulation. A selective data capture method is proposed in this paper that only captures debug data during clock cycles in which errors are present. The proposed debug method requires only three debug sessions. The first session estimates a rough error rate, the second session identifies a set of suspect clock cycles where errors may be present, and the third session captures the suspect clock cycles in the trace buffer. The suspect clock cycles are determined through a 2-D compaction technique using multiple-input signature register signatures and cycling register signatures. Intersecting both signatures generates a small number of suspect clock cycles for which the trace buffer needs to capture. The effective observation window of the trace buffer can be expanded significantly, by up to orders of magnitude. Experimental results indicate very significant increases in the effective observation window for a trace buffer can be obtained.

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

In multi-core designs, distributed embedded logic analyzers with multiple trigger units and trace buffers with real-time offload capability through high-speed trace ports can be placed on-chip. This brings new challenges on how to connect the debug units together in such way that the limited storage space in the trace buffers can be used efficiently. This problem is further aggravated when shadow registers are used to capture data for some signals in the design. In this paper, we propose a new architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple data sources and user-programmable priorities. Experimental results show that using the proposed architecture, real-time observability can be improved using only a small amount of on-chip logic hardware, while avoiding excessive storage on-chip.

Real-Time Lossless Compression for Silicon Debug

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Silicon debug is becoming a key step in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the lack of observability for the internal circuit nodes during silicon debug, embedded logic analysis enables real-time data acquisition from a limited number of internal signals. In this paper, we propose a novel architecture for embedded logic analysis that enables real-time lossless compression of debug data. To quantify the gain from using lossless compression in embedded logic analysis, we present a new compression-ratio metric that captures the trade-off between the area and the increase in the observation window. The proposed architecture is particularly suitable for in-field debugging on application boards, which have asynchronous events that inhibit the deterministic replay of debug experiments. </para>

Comprehensive Approach to High-Performance Server Chipset Debug

This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.