Memory Deallocation Research Articles

SafeMD: Ownership-Based Safe Memory Deallocation for C Programs

Rust is a relatively new programming language that aims to provide memory safety at compile time. It introduces a novel ownership system that enforces the automatic deallocation of unused resources without using a garbage collector. In light of Rust’s promise of safety, a natural question arises about the possible benefits of exploiting ownership to ensure the memory safety of C programs. In our previous work, we developed a formal ownership checker to verify whether a C program satisfies exclusive ownership constraints. In this paper, we further propose an ownership-based safe memory deallocation approach, named SafeMD, to fix memory leaks in the C programs that satisfy exclusive ownership defined in the prior formal ownership checker. Benefiting from the C programs satisfying exclusive ownership, SafeMD obviates alias and inter-procedural analysis. Also, the patches generated by SafeMD make the input C programs still satisfy exclusive ownership. Usually, a C program that satisfies the exclusive ownership constraints is safer than its normal version. Our evaluation shows that SafeMD is effective in fixing memory leaks of C programs that satisfy exclusive ownership.

SafeDrop: Detecting Memory Deallocation Bugs of Rust Programs via Static Data-flow Analysis

Rust is an emerging programming language that aims to prevent memory-safety bugs. However, the current design of Rust also brings side effects, which may increase the risk of memory-safety issues. In particular, it employs ownership-based resource management and enforces automatic deallocation of unused resources without using the garbage collector. It may therefore falsely deallocate reclaimed memory and lead to use-after-free or double-free issues. In this article, we study the problem of invalid memory deallocation and propose SafeDrop , a static path-sensitive data-flow analysis approach to detect such bugs. Our approach analyzes each function of a Rust crate iteratively in a flow-sensitive and field-sensitive way. It leverages a modified Tarjan algorithm to achieve scalable path-sensitive analysis and a cache-based strategy for efficient inter-procedural analysis. We have implemented our approach and integrated it into the Rust compiler. Experiment results show that the approach can successfully detect all such bugs in our experiments with a limited number of false positives and incurs a very small overhead compared to the original compilation time.

Managing heterogeneous device memory using C++17 memory resources

Programmers using the C++ programming language are increasingly taught to manage memory implicitly through containers provided by the C++ standard library. However, heterogeneous programming platforms often require explicit allocation and deallocation of memory. This discrepancy in memory management strategies can be daunting and problematic for C++ developers who are not already familiar with heterogeneous programming. The C++17 standard introduces the concept of memory resources, which allow the user to control how standard library containers allocate memory; we believe that this addition to the C++17 standard is a powerful tool towards the unification of memory management for heterogeneous systems with best-practice C++ development. In this paper, we present vecmem, a library of memory resources which allows efficient and user-friendly allocation of memory on CUDA, HIP, and SYCL devices through standard C++ containers. We investigate the design and use cases of such a library, the potential performance gains over naive memory allocation, and the limitations of this memory allocation model.

Automatic proofs of memory deallocation for a Whiley-to-C Compiler

Automatic proofs of memory deallocation for a Whiley-to-C Compiler

Robustness of Differentiable Neural Computer Using Limited Retention Vector-based Memory Deallocation in Language Model

Recurrent neural network (RNN) architectures have been used for language modeling (LM) tasks that require learning long-range word or character sequences. However, the RNN architecture is still suffered from unstable gradients on long-range sequences. To address the issue of long-range sequences, an attention mechanism has been used, showing state-of-the-art (SOTA) performance in all LM tasks. A differentiable neural computer (DNC) is a deep learning architecture using an attention mechanism. The DNC architecture is a neural network augmented with a content-addressable external memory. However, in the write operation, some information unrelated to the input word remains in memory. Moreover, DNCs have been found to perform poorly with low numbers of weight parameters. Therefore, we propose a robust memory deallocation method using a limited retention vector. The limited retention vector determines whether the network increases or decreases its usage of information in external memory according to a threshold. We experimentally evaluate the robustness of a DNC implementing the proposed approach according to the size of the controller and external memory on the enwik8 LM task. When we decreased the number of weight parameters by 32.47%, the proposed DNC showed a low bits-per-character (BPC) degradation of 4.30%, demonstrating the effectiveness of our approach in language modeling tasks.

An algorithmic approach for performance tuning of a relational database system using dynamic SGA parameters

In twenty-first century, spatial database are becoming complex in nature due to the diversity of resources to generate and collect these datasets. Efficient query handing and high performance is the key requirement for success for the expert systems (like GIS) using these spatial databases. However, relational database management systems (RDBMS) used for storing spatial datasets are struggling for auto-tuning, self-diagnosis and self-healing. To overcome these challenges for spatial database and RDBMS, we have identified 250 plus dynamic parameters, which are responsible for managing SGA (system global area) of a running instance of any RDBMS. These parameters can be controlled at runtime and allocation and deallocation of memory to the various components of SGA can be managed by changing the values of these parameters. In this research work, the data is collected related to the system parameters and the resources utilized by the system. The collected data is automatically analyzed to find the relation between parameters and resources. Based upon the relations (direct or inverse) the decision will be taken by the developed utility to enhance overall system performance. In this work a framework, related algorithms, and utility tool to perform above-said steps for improving performance are designed and implemented. This research work will help to get fast and efficient handling of spatial datasets, which will directly affect the performance of expert system to take quick decisions.

Language Model Using Differentiable Neural Computer Based on Forget Gate-Based Memory Deallocation

A differentiable neural computer (DNC) is analogous to the Von Neumann machine with a neural network controller that interacts with an external memory through an attention mechanism. Such DNC’s offer a generalized method for task-specific deep learning models and have demonstrated reliability with reasoning problems. In this study, we apply a DNC to a language model (LM) task. The LM task is one of the reasoning problems, because it can predict the next word using the previous word sequence. However, memory deallocation is a problem in DNCs as some information unrelated to the input sequence is not allocated and remains in the external memory, which degrades performance. Therefore, we propose a forget gate-based memory deallocation (FMD) method, which searches for the minimum value of elements in a forget gate-based retention vector. The forget gate-based retention vector indicates the retention degree of information stored in each external memory address. In experiments, we applied our proposed NTM architecture to LM tasks as a task-specific example and to rescoring for speech recognition as a general-purpose example. For LM tasks, we evaluated DNC using the Penn Treebank and enwik8 LM tasks. Although it does not yield SOTA results in LM tasks, the FMD method exhibits relatively improved performance compared with DNC in terms of bits-per-character. For the speech recognition rescoring tasks, FMD again showed a relative improvement using the LibriSpeech data in terms of word error rate.

Hardware Dynamic Memory Manager for Hard Real-Time Systems

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

Joint forces for memory safety checking revisited

We present an improved version of the memory safety verification approach implemented in Symbiotic 5, the winner of the MemSafety category at the Competition on Software Verification (SV-COMP) 2018. The approach can verify programs for standard errors in memory usage like invalid pointer dereference or memory leaking. It is based on instrumentation, static pointer analysis extended to consider memory deallocations, static program slicing, and symbolic execution. The improved version brings higher precision of the extended pointer analysis and further optimizations in instrumentation. It is implemented in the current version of Symbiotic, which contains also some improvements in program slicing and symbolic execution. We explain the approach in theory, describe implementation of selected components, and provide experimental results showing the impact of particular components.

Comprehensive performance analysis of C++ smart pointers

Smart pointers play an important role in bypassing memory leaks in C++. Since C++11 standard the smart pointers have become widely-used tools because they let the programmers not to deal with memory deallocation. However, abstraction penalty occurs because of this convenience. Overhead is related to runtime, memory usage and compilation time. There are many different smart pointers in the standard library. However, the performance difference between the smart pointers and raw pointers is not measured before. This paper presents an analysis of their effectiveness. An alternative approach to the C++17’s optional construct is searched for.

Optimizing Memory Usage in L4-Based Microkernel

Memory allocation is a critical aspect of any modern operating system kernel because it must run continuously for long periods of time, therefore memory leaks and inefficiency must be eliminated. This paper presents different memory management algorithms and their aplicability to an L4-based microkernel. We aim to reduce memory usage and increase the performance of allocation and deallocation of memory.

ROBUST MEMORY MANAGEMENT USING REAL TIME CONCEPTS

Memory fragmentation is the development of a large number of separate free areas. Memory management in embedded systems demand effective implementation schemes to avoid fragmentation problem. Existing dynamic memory allocation methods fail to suit real time system requirements. Execution times need to be deterministic and this motivates the need for allocation and deallocation to be done in constant time with the help of API’s. In I¼C/OS-II, memory allocation is semi-dynamic and a buddy allocator dynamic memory allocation algorithm is commonly used. Programmer must statically allocate a memory and partition the region using I¼C/OS-II Kernel API. Tasks can only request pre-partitioned fixed-size memory space from I¼C/OS-II. Memory allocation times are influenced by the ratio of memory allocation to the stack size of the task. In this research work memory management in LPC 1768 environment using RTOS I¼C/OS-II is proposed. Effective sharing of memory blocks among tasks co exists with partition. The captured results shows that the memory allocation and deallocation suits real time. The implication of the work is that, the necessity to reserve a static set of locations ahead of time is eliminated so that memory can be allocated at compile or design time.

This Isn't Your Parents' Fortran: Managing C++ Objects with Modern Fortran

Modern Fortran automates dynamic memory deallocations, except in two cases: memory allocated via pointers and via a second language at the request of a Fortran driver. This article focuses on the second exception and presents a reference-counting architecture that requires minimal user intervention to safely free memory if and only if no references remain.

Backwards type analysis of asynchronous method calls

Asynchronous method calls have been proposed to better integrate object orientation with distribution. In the language, asynchronous method calls are combined with so-called processor release points in order to allow concurrent objects to adapt local scheduling to network delays in a very flexible way. However, asynchronous method calls complicate the type analysis by decoupling input and output information for method calls, which can be tracked by a type and effect system. Interestingly, backwards type analysis simplifies the effect system considerably and allows analysis in a single pass. This paper presents a kernel language with asynchronous method calls and processor release points, a novel mechanism for local memory deallocation related to asynchronous method calls, an operational semantics in rewriting logic for the language, and a type and effect system for backwards analysis. Source code is translated into runtime code as an effect of the type analysis, automatically inserting inferred type information in method invocations and operations for local memory deallocation in the process. We establish a subject reduction property, showing in particular that method lookup errors do not occur at runtime and that the inserted deallocation operations are safe.

Typed memory management via static capabilities

Region-based memory management is an alternative to standard tracing garbage collection that makes operation such as memory deallocation explicit but verifiably safe. In this article, we present a new compiler intermediate language, called the Capability Language (CL), that supports region-based memory management and enjoys a provably safe type systems. Unlike previous region-based type system, region lifetimes need not be lexically scoped, and yet the language may be checked for safety without complex analyses. Therefore, our type system may be deployed in settings such as extensible operating systems where both the performance and safety of untrusted code is important. The central novelty of the language is the use of static capabilities to specify the permissibility of various operations, such as memory access and deallocation. In order to ensure capabilities are relinquished properly, the type system tracks aliasing information using a form of bounded quantification. Moreover, unlike previous work on region-based type systems, the proof of soundness of our type system is relatively simple, employing only standard syntactic techniques. In order to show how our language may be used in practice, we show how to translate a variant of Tofte and Talpin's high-level type-and-effects system for region-based memory management into our language. When combined with known region inference algorithms, this translation provides a way to compile source-level languages to CL.

On Memory-Block Traversal Problems in Model Checking Timed Systems

A major problem in model-checking timed systems is the<br />huge memory requirement. In this paper, we study the memory-block<br />traversal problems of using standard operating systems in exploring the<br />state-space of timed automata. We report a case study which demonstrates<br />that deallocating memory blocks (i.e. memory-block traversal)<br />using standard memory management routines is extremely time-consuming.<br />The phenomenon is demonstrated in a number of experiments by<br />installing the Uppaal tool on Windows95, SunOS 5 and Linux. It seems<br />that the problem should be solved by implementing a memory manager<br />for the model-checker, which is a troublesome task as it is involved in<br />the underlining hardware and operating system. We present an alternative<br />technique that allows the model-checker to control the memory-block<br />traversal strategies of the operating systems without implementing<br />an independent memory manager. The technique is implemented in the<br />Uppaal model-checker. Our experiments demonstrate that it results in<br />significant improvement on the performance of Uppaal. For example, it<br />reduces the memory deallocation time in checking a start-up synchronisation<br />protocol on Linux from 7 days to about 1 hour. We show that the<br />technique can also be applied in speeding up re-traversals of explored<br />state-space.

Fast allocation and deallocation of memory based on object lifetimes

AbstractDynamic storage‐management algorithms are based either on object sizes or object lifetimes. Stack allocation, which is based on object lifetimes, is the most efficient algorithm, but severely restricts object lifetimes and creation times. Other algorithms based on object sizes, such as first fit and related algorithms, permit arbitrary lifetimes but cost more. More efficient variations capitalize on application‐specific characteristics. Quick fit, for example, is more efficient when there are only a few object sizes. This paper describes a simple algorithm that is very efficient when there are few object lifetimes. In terms of instructions executed per byte allocated, the algorithm is almost half the cost of quick fit and less than twice the cost of stack allocation. Space for all objects with the same lifetime is allocated from a list of large arenas, and the entire list is deallocated at once. An implementation in ANSI C is included.