DC Path Research Articles

Battery‐free ultra‐low‐power radio‐frequency receiver for mm‐wave applications using 130‐nm CMOS technology with harvested DC supplies

SummaryThis paper presents a battery‐free ultra‐low‐power (ULP), highly integrated, and wide‐bandwidth low‐IF radio‐frequency (RF) receiver designed for millimeter‐wave (mm‐Wave) applications, utilizing 130‐nm CMOS technology. The suggested RF receiver is suitable for K‐band (n258) at 26 GHz, Ka‐band (n261 and n257) at 28 GHz, and the LMDS band at 28 GHz in fifth‐generation applications. The proposed radio receiver consists of a low‐noise driver stage implemented using a complementary current‐reuse common gate with an active shunt feedback configuration and an in‐phase/quadrature‐phase (I/Q) demodulator. The proposed RF receiver employs transformer coupling to isolate the DC path between the transconductance stage (RF stage) and the switching stage (IF stage). The driver stage expands the RF input impedance while maintaining acceptable linearity and gain with ultra‐low DC power dissipation. The DC supplies for the proposed mm‐Wave RF receiver are generated using two novel energy‐harvesting voltage doubler circuits to provide positive and negative voltages. The proposed mm‐Wave radio receiver consumes 0.475 mW from a 1.1 V DC supply and exhibits a power conversion gain (CG) of 6.3 dB, with a 3 dB frequency bandwidth extending from 22 to 32 GHz. The input 1‐dB compression point (P1dB) of the RF receiver is −2.65 dBm, and the input third‐order intercept point (IIP3) is 7.35 dBm. With a sensitivity of −66.5 dBm at a 100 MHz channel bandwidth and a dynamic range of 63.85 dB, the suggested receiver demonstrates notable performance characteristics. The proposed radio receiver boasts an excellent figure of merit (FoM) at 215 dB, surpassing published works by a margin of 8–31 dB. The primary positive supply voltage is derived from a double‐band positive voltage doubler with series resonance feedback and parallel resonance networks, efficiently achieving the desired DC voltage and output current (1.1 V and 450 μA). Meanwhile, the negative gate bias is provided by a negative voltage doubler, ensuring the necessary negative voltage (−0.5 V) without any current conditions.

An integrated thermal and RF energy harvesting system with rectifying combination and storage controller for IoT devices

This work presents an integrated thermal/RF energy harvester. The harvesting system can combine energy from two sources simultaneously (one DC and one AC) and deliver a regulated combined voltage of 1.75 V to a load and a storage controller. The output power of the harvester is in the range of hundreds of μWatts which is suitable for low-power wireless sensor networks. Maximum power point tracking (MPPT) is achieved by reconfiguring the number of stages of the DC path, the frequency driving the charge pump, and the capacitors of the matching network in the RF-path. The storage controller charges a supercapacitor to 3.5 V to power up the system during power shortage periods. The system is implemented in a 180 nm CMOS technology and utilizes a total on-chip capacitance of 2.4 nF. The peak end-to-end efficiency of the system reaches 60.3 % at output load power of 1.275 mW.

Modeling and Current Control Strategy for Novel Two-Phase DC-Biased Vernier Reluctance Machine

This paper proposes a drive topology and vector control strategy for a two-phase DC-biased vernier reluctance machine (DCB-VRM) with non-overlapping windings. Since the DC path needs to be reserved in the DCB-VRM drive topology, more power switching devices are needed in theory. In order to generate DC bias sinusoidal current and reduce costs, a low-cost drive topology is applied. The machine's mathematical model in the stationary and synchronous rotating frame is derived. Then the vector control strategy is proposed. Through effective control of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dqdc</i> -axis currents, maximum torque per ampere (MTPA) can be achieved. The resonant controllers are paralleled with the proportional-integral (PI) controller to suppress current harmonics in the control method. Finally, the simulation and experimental results validate that the proposed drive topology and control strategy can effectively control the two-phase DCB-VRM.

Decoupled Control Scheme for THD Reduction and One Specific Harmonic Elimination in the Modular Multilevel Converter

This article proposes a decoupled control scheme for the modular multilevel converter (MMC) to reduce the total harmonic distortion (THD) and eliminate one specific harmonic. First, to realize the decoupled control between the ac and dc paths of the MMC, an improved nearest level control (INLC) method is proposed. It applies the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">round</i> function to generate the ac output voltage levels, instead of the arm output voltage levels. Thus, a staircase wave is generated by the INLC method. Then, by adding an additional pulse to each quarter of the staircase wave, one specific harmonic can be eliminated without optimizing each conduction angle. Furthermore, a decoupled circulating current fuzzy control method is proposed to suppress the second-order harmonic and balance the arm energy. By this decoupled control structure, the output voltage and the circulating current can be controlled independently. Taking the fifth-order harmonic as an example, simulation and experimental results validate that the proposed scheme can simultaneously realize THD reduction and one specific harmonic elimination in the MMC output voltage.

A 135–150 GHz High-Power Frequency Tripler With Filtering Matching Network

This letter presents a 135–150 GHz high-efficiency and -power Schottky diode-based tripler integrated with low-loss waveguide filtering matching network. The active diode monolithic microwave integrated circuit (MMIC) is matched with two waveguide filters based on coupling matrix theory for a two-port network with complex impedance terminations. The filters and the active diode MMIC are integrated via the microstrip-to-waveguide transition, allowing a compact design on the relatively higher loss MMIC. In addition, an integrated on-chip capacitor is implemented to isolate dc and RF paths. The measurement shows that with 150–200 mW input power, the maximum conversion efficiency reaches 30.5% and the maximum output power is 47 mW. All filtering poles can be observed in measurements and the return loss achieves 10–15 dB within the passband. Good agreements between measurements and simulations demonstrate the validity of the design approach.

DESIGN AND SIMULATION OF LOW POWER, HIGH GAIN AND HIGH BANDWIDTH CMOS FOLDED CASCODE OTA USING RECYCLING AND gm/ID TECHNIQUE

This paper includes the design of Enhanced Recycling folded cascode Operational Transconductance Amplifier (ERFC OTA) in both strong inversion and moderate inversion. The primary motivation for the design is from standard folded cascade (FC) OTA. The biased current sources are not contributing to the Transconductance (Gm) of the OTA in the usual FC OTA. In the Recycling FC OTA, the currents are recycled and the biased current sources are made to contribute to the Gm of the OTA and so the Gm is increased. Gm is further enhanced in Improved RFC OTA by creating one more high impedance dc path to the RFC architecture. The design is implemented in 90 nm UMC CMOS technology.

A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme

This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, i.e., 4T2C, for minimal area penalty and full logic compatibility. The FeCAP with 10-nm-thick Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film shows excellent ferroelectricity (Pr = 15 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and good memory characteristics (cycles 1011). The 4T2C nvSRAM is capable of storing and restoring previous memory states for nonvolatile data storage. To compensate the leakage current in the dynamic nodes of 4T load less SRAM, we propose a dynamic current compensation operation scheme by exploiting the polarization-dependent leakage current of FeCAP. Outstanding characteristics were achieved in this nvSRAM cell: 1) elimination of the dc path; 2) ultralow store and restore power consumption; and 3) high area efficiency.

Speed Control for DC Encoder Motor and Path Optimization in an Automated Guided Vehicle

Automated guided vehicle （AGV） has variety of applications in the field of automotive and logistics. For stability of plant AGV should run at a constant speed. The AGV incorporates DC encoder motor which is controlled by Fuzzy controller and PID controller to acquire the constant speed. Response of the system with of fuzzy controller and PID controller is done. . The steady state error and overshoot of the system is reduced by the fuzzy logic controller. Dijkstra’s algorithm is applied to find an optimal path. This algorithm finds the shortest path between the source node and destination node.

Low Noise Programmable DC Amplifier with Remote Control

Introduction. In modern experimental technology, the direction associated with the development of information-measuring systems for recording, pre-processing and analyzing excess low-frequency noise (flicker noise) is well known. Currently, such measuring systems are mainly presented in the form of particular solutions, due to the large variety of research goals and objectives. At the same time, for automation of the experiment, multichannel measuring complexes with the possibility of flexible reconfiguration of the measuring channel according to the task are highly demanded. It is obvious that any distributed measuring channel is represented as a multi-stage scheme with given functions and parameters of each stage, which makes it difficult for the measuring system to adapt to different conditions and tasks of the experiment. The logical solution to this problem is a deep unification of all components of the measuring channel while maintaining good performance characteristics. One of the main problems with this is the evaluation of the intrinsic noise of electronic elements, which provide for changing the parameters of the amplifier.Objective. Experimental analysis of the intrinsic noise of electronic potentiometers, development of the concept and study of parameters of a low-noise DC amplifier with a high degree of unification, the possibility of external electronic control and the use of built-in characteristics correction algorithms.Materials and methods. To achieve the set result, a method for measuring the noise of electronic potentiometers was proposed and experimental studies were carried out.Results. According to the calculation results and experimental studies, it was shown that the specific noise of the electronic potentiometers corresponds to the noise of the metal-film resistors, which makes it possible to use them in low-noise amplification stages. The developed circuit solutions allow the implementation of a unified amplifying module with cascading to build low-noise measuring DC paths based on electronic potentiometers. External and internal digital control allows you to significantly improve the performance of the measuring path as a whole and allows you to adapt it to a wide range of tasks.Conclusion. As part of the study, a method was proposed for measuring the noise of electronic potentiometers, analytical and experimental studies were carried out, and a prototype of a low-noise amplifier was developed and investigated.

Research on Optimal placement for GIC mitigation with Blocking Device

Geomagnetically induced current (GIC) caused by geomagnetic storms flows between the power grid and the earth would threaten the stable operation of the power system. Capacitor blocking device connected in series at transformer neutral point can directly block the DC path. However, due to the complexity of the DC path in the power system, before the installation of the blocking device, if global considerations are not taken into account, the adverse effects of GIC will not be reduced. Therefore, to study the position optimization of the capacitor blocking device is of great value. This optimization of placement of capacitor blocking device is proposed in this paper. Applying the idea of genetic algorithm, the installation quantity and installation position of the blocking device were calculated and compared with the traditional GIC non-optimal method, which verified the superiority of the genetic algorithm optimization solution.

High-Accuracy Localization of Passive Tags With Multisine Excitations

This paper proposes an extensive study of multisine excitations to enable high-accuracy localization of battery-less tags, by harvesting the higher order harmonics, generated by the rectifier nonlinearity. Usually, these harmonics are either filtered out or terminated, to increase the conversion efficiency. A dual-mode rectifier with the output section splitted into two paths is designed. One dc path is the common one used to deliver the converted dc power to an optimum load and the second path is broadband and collects the higher harmonics obtaining an ultrawideband radiated signal to communicate with the receivers for tag localization. To this purpose, a variety of multisine excitation signals, with different tones, spacing among tones and bandwidth, is accurately evaluated to characterize the system-level localization performance. Both the modeled and experimental results are presented demonstrating the excellent performance of such a dual-mode rectifier, despite of the limited add-on circuitry if compared to those used in standard rectennas. For an average received power of −10 dBm, measurements show that the localization of a tag with centimeter-level accuracy can be achieved at more than 10 m distance from the receivers having a 4 dB noise figure.

Robust Coverless Image Steganography Based on DCT and LDA Topic Classification

In order to improve the robustness and capability of resisting image steganalysis, a novel coverless image steganography algorithm based on discrete cosine transform and latent dirichlet allocation (LDA) topic classification is proposed. First, latent dirichlet allocation topic model is utilized for classifying the image database. Second, the images belonging to one topic are selected, and 8 × 8 block discrete cosine transform is performed to these images. Then robust feature sequence is generated through the relation between direct current coefficients in the adjacent blocks. Finally, an inverted index which contains the feature sequence, dc , location coordinates, and image path is created. For the purpose of achieving image steganography, the secret information is converted into a binary sequence and partitioned into segments, and the image whose feature sequence equals to the secret information segments is chosen as the cover image according to the index. After that, all cover images are sent to the receiver. In the whole process, no modification is done to the original images. Experimental results and analysis show that the proposed algorithm can resist the detection of existing steganalysis algorithms, and has better robustness against common image processing and better ability to resist steganalysis compared with the existing coverless image steganography algorithms. Meanwhile, it is resistant to geometric attacks to some extent. It has great potential application in secure communication of big data environment.

A low-power D flip flop integrated by metal oxide thin film transistors employing internal feedback control

The conventional D flip flop (DFF) consists of six pseudo-CMOS NOR gates integrated by monotype transistors. By analyzing the six logic states of the conventional DFF, it is found that the three-input NOR gate can be replaced by a new three-input NOR gate with a pull-up control signal and the pull-up control signal is connected to an output of another NOR gate. As a result, a new DFF is developed by using such an internal feedback control method. The static power consumption can be reduced by cutting off the dc path properly in the proposed DFF. For comparison, the conventional DFF and the proposed DFF are both fabricated by metal oxide thin film transistors with an etch stop layer structure on the basis of the same design parameters. Both the conventional DFF and the proposed DFF have the same function and both work using the negative edge triggered method. The measured power consumption of the proposed DFF is at least 13% less than that of the conventional DFF under the condition of a 20 kHz clock signal.

Relay based Coupling Scheme of High Speed Communication data, High voltage DC And High Power Pulsed AC for Coaxial Cable

Coaxial cable telemetry is most commonly used in the field of underwater applications like data logging in oil rigs, underwater wireless modem, underwater acoustic measurements, borehole measurements, deep sea telemetry for sediment analysis, airborne sonars, imaging sonars etc. In all the above applications coaxial multicore cables are used. The design and development of relay based coupling scheme which helps to replace the multi core cable with a single core coaxial cable for telemetry application is described. Single core cable is suitable for long distance data communication. Multi core cables are generally heavy and due to the size, may not meet space constraints in complex systems. They are not economical too. The relay based coupling scheme is used to mix or separate the high speed bi-directional communication data, high voltage DC and high power pulsed AC. In single relay scheme one relay is used to switch the centre core of single core coaxial cable. Here the ground is common for both high power AC transmission and high speed bi-directional data path. A dual relay scheme is discussed where two relays are used to switch both the centre core and ground of the single core coaxial cable. This provides more ground isolation and can avoid ground lifting issues while high power AC transmission occurs. The simulation of the coupling scheme was done using PSpice®. A prototype of the coupling scheme was also made for analysis. Filter responses were analysed for each coupling path. The DC coupling filter has 85 Hz cut-off frequency at -3 dB. The cut-off frequency of high speed data coupler is 500 KHz at -3 dB. A 4.3KV peak to peak of 3 KHz and 7 KHz AC signals were transmitted and measurements were taken to analyse the effect of high voltage over different coupling paths. The 3 KHz signal has a peak of 61.88 dB and that of 7 KHz signal, the peak is 62.50 dB. The signal components of 3 KHz signal in the DC path has a voltage level of 9.375 dB and that of 7 KHz signal is 25.63 dB.

Bandwidth Enhancement Utilizing Bias Circuit as Parasitic Elements in a Reconfigurable Circularly Polarized Antenna

A circularly polarized (CP) crossed-dipole antenna with switchable rotating sense is presented. The proposed design has two main attractive features. First, a wide overlapped CP bandwidth (BW) is realized for both operating states. Second, unlike existing designs targeting a similar functionality, no biasing wire through ground plane is required, which significantly reduces the design complexity. The proposed design employs parasitic elements for two different roles. For RF signal, these parasitic elements open an additional CP resonance band to enhance the axial-ratio (AR) BW. Additionally, through RF chokes, they provide a dc path to bias the p-i-n diodes. An antenna prototype was experimentally demonstrated with the capability of switching between two CP rotating senses in a frequency range from 1.1 to 2.02 GHz, equivalent to 58.9%. The antenna also exhibits a wide −10 dB impedance BW of 53.3% (1.1–1.9 GHz) with a peak gain of around 9.1 dBi and front-to-back ratio of more than 15 dB.

Visible Light Communication Channel Modeling for Underwater Environments With Blocking and Shadowing

In this paper, we present a comprehensive channel modeling and characterization study for underwater visible light communications. Our study is based on the advanced ray tracing, which allows for an accurate description of the interaction of rays emitted from the lighting source within an underwater environment. Contrary to existing works, which are mainly limited to simplified underwater scenarios, i.e., empty sea, we take into account the presence of human and man-made objects to investigate the effects of shadowing and blockage. The reflection characteristics of the sea surface and sea bottom as well as the water characteristics, i.e., extinction coefficient and scattering phase function of particles, are precisely considered. As case studies, we consider various underwater scenarios with different transmitter/receiver specifications (i.e., viewing angle, aperture size) and different depths from the sea surface. For each environment, we obtain channel impulse responses and present a characterization study where channel parameters, such as channel DC gain, path loss, and delay spread, are obtained.

Electronically Reconfigurable Notch Filter for Cognitive Radios Application

An electronically reconfigurable notch filter for cognitive radios application is presented. By loading the stub-loaded resonator along the transmission line, two notched bands are created. Central frequency tuning of one notched band is realized by using the silicon varactor diodes, while the other notched band remains almost unchanged during tuning. Bias Ts and the resistors having high resistance value are adopted to function as DC paths for the varactors. A tuning range of 1.92–2.92 GHz for the one notched band with average insertion loss 2.4 dB across the passband (0.1–5 GHz) is achieved, and the other notched band is used to suppress the WiMAX signal (3.3– 3.8 GHz). The highest rejection level of the tunable notched band is 21.5 dB, while the static notched band shows rejection of more than 30 dB at 3.66 GHz.

Flexible Antenna Integrated With an Epitaxial Lift-Off Solar Cell Array for Flapping-Wing Robots

We describe the integration of a flexible UHF antenna with an epitaxial lift-off thin-film III-V solar cell array used for power generation and wireless communication in a flapping-wing robotic platform. The antenna is configured to utilize the cells and their interconnections as a part of the radiating element, leading to compact multifunctional antenna/solar cell array surface. The high junction capacitance of individual solar cells allows RF current conduction through the cells without an associated power penalty. Metallic interconnects in the solar cell array carry both the DC power as well as forming part of the UHF antenna. To suppress RF current leakage into the DC circuit used for conducting the solar cell current, a RF choke is inserted between the antenna and the solar cells in the DC path. The performance characteristics of the integrated antenna and solar cell array verify the predicted performance of the antenna for reliable communication. Further, mounting the thin film solar cell array on a 25 μm thick Kapton sheet is shown to be a robust power source when positioned on the flexible wings of flapping robotic platforms. Details about design procedure and performance of the proposed integrated antenna are discussed.

An inductive-degenerated current-bleeding LNA-merged CMOS mixer for 866 MHz RFID reader

This paper presents a new LNA merged mixer topology with improved linearity and noise figure for 866 MHz UHF RFID reader. A novel technique of inductive degeneration of the current bleeding PMOS devices has been utilized to reduce the RF signal leakage through this DC path. This technique along with common-mode inter-modulation feedback and tail capacitance tuning is employed to achieve the superior performance. The mixer was implemented in 130 nm IBM CMOS process and achieved an IIP3 of ?4.1 dBm, a DSB noise figure of 7.5 dB along with a flicker noise 1/f corner frequency of 45 kHz. In addition, with the noise and power matched merged LNA/transconductor, an S11 of ?19.1 dB and an RF-to-IF conversion gain of 17 dB was achieved using a 1.2 V supply. The mixer occupied a silicon area of only 0.54 sq. mm which includes all the center-tapped degeneration and stray tuning inductors.

A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

A 0.5---2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5---2.5 GHz band. The noise figure (NF) is 3.9---5.0 dB and the IIP3 is 3.1---3.6 dBm. The power consumption is only 910 uW.