DC Pads Research Articles

A 32-GHz Eight-Way Power Amplifier MMIC in 150 nm GaN HEMT Technology

This paper presents a 32 GHz high-power amplifier (HPA) with a design strategy to achieve high-power output with reliable operation for Ka-band deep space satellite communication in 150 nm GaN HEMT technology. The presented Ka-band HPA employs a cascaded two-stage common source amplifier topology, and the output stage comprises an eight-way power combining network in the current mode. The interstage matching network is designed with the bandpass configuration utilizing capacitors and transmission lines to provide better stability at the low-frequency regime. The implemented Ka-band HPA achieved a power gain of 7.3 dB at the input level with the maximum PAE at 32 GHz, and the 3 dB gain bandwidth was 3.5 GHz (31.3~34.8 GHz). The saturated output power at the peak power-added efficiency (PAE) of 19.3% was 38.2 dBm, and the output 1 dB gain compression point (OP1 dB) was 27.4 dBm in the measurement. The designed HPA consumes an area of 19.35 mm2 including RF pads and DC pads.

A wideband accurate compact 6‐bit phase shifter in 0.15‐μm GaAs technology

AbstractA Ku wideband accurate compact 6‐bit digital phase shifter is designed in this letter using three different switched phase shift structures: the switched L/C structure, T‐type structure, and high‐pass/low‐pass network. To improve the bandwidth and the gain flatness, an improved switched L/C structure is used and the systematic cascade sequence of the phase shifter is optimized. The improved switched L/C structure solves the problem that conventional L/C networks are hypersensitive to the coupling capacitance at high‐frequency input. As a result, the improved L/C structure can achieve wideband and better s‐parameters. The proposed 6‐bit switched phase shifter is implemented in 0.15‐μm GaAs pHEMT process. The measured root‐mean‐square (rms) phase error is less than 2.8° at 12–18 GHz, and the average insertion loss (IL) is 6.5–6.9 dB. The chip size of the proposed 6‐bit digital phase shifter is 3.1 × 1 mm2, including all RF and dc pads, which is very suitable for radar systems.

K 대역 위성통신용 CMOS 저잡음 증폭기 설계

This study entailed the design of a K-band low noise amplifier (LNA) by using the 65-nm bulk CMOS process. In the designed low noise amplifier, a large transistor was used to reduce the size of the lossy gate series inductor, resulting in low noise and high gain. In addition, the source generation and shunt inductors were used at the input stage to enable simultaneous noise and input matching. The LNA had a size of 0.67×0.39 mm2 including RF and DC pads. A peak gain of 19.5 dB and a minimum noise figure of 2.31 dB were achieved. Owing to the design, the input and output return loss was more than 10 dB at 17~23 GHz.

A 208–233-GHz Frequency Doubler With 1.1% Power-Added Efficiency in 28-nm CMOS

This letter presents a fully integrated frequency doubler in the TSMC 28-nm CMOS technology. MOS transistor capacitor neutralization is introduced in the differential driving amplifier, which shows better robustness than MOM capacitor neutralization under PVT variations. Besides, a stacked transformer-based balun is designed to achieve good balance performance. The effect of dummy metal on the performance of the proposed balun is also discussed. The measured results show that the 3-dB bandwidth is 25 GHz (208–233 GHz) and the peak power-added efficiency is 1.1% with a dc power consumption of 26.4 mW at 222 GHz. The peak conversion gain is −7.2 dB and the variation in conversion gain is less than 1 dB within −7- to 1-dBm input power range. Moreover, the chip size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$492\times 412\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> , including GSG and DC pads.

위성통신을 위한 K-Band 전력 증폭기

This study entailed the development of a K-Band power amplifier (PA). The proposed PA was implemented and verified using a 65-nm bulk CMOS process. The PA was designed with two stages to obtain sufficient gain in the K band. The PA had a chip area of 0.93×0.47 mm2 including RF and DC pads. The manufactured power amplifier design had a maximum saturation power of 22.4∼22.7 dBm in the 19–21 GHz frequency band, and a power added efficiency (PAE) of 39 %∼40 %. In the two-tone simulation results, the linear power and efficiency levels satisfying third-order inter-modulation distortion (IMD3) below −30 dBc were confirmed to be 16∼17 dBm and 24%∼26 % in the 19∼21 GHz frequency band, respectively.

An X/Ku Dual-Band Switchless Frequency Reconfigurable GaAs Power Amplifier

This letter presents an <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>/ <i>Ku</i> dual-band switchless power amplifier (PA) with frequency reconfigurable operation in a 0.25-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. The proposed reconfigurable PA consists of one dual-band drive amplifier and two single-band amplifiers in parallel. The first stage drive amplifier works in dual-band mode of <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-band and <i>Ku</i>-band, and the two single-band amplifiers work in <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-band and <i>Ku</i>-band, respectively. An interstage coupled line is used to split the dual-band frequencies into high-band (<i>Ku</i>-band) and low-band (<inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-band), and the output-stage coupled line acts as a combiner. The operating frequency band of the proposed PA can be changed by turning off drain voltages of unused single-band amplifiers. Measurements results show that the proposed reconfigurable PA features a maximum power-added efficiency (PAE) of 44.4&#x0025; and a power gain of 19.6 dB while delivering an output power of 29.6 dBm at 8.5&#x2013;9.5 GHz of the low-band mode. At 15.5&#x2013;16.5 GHz of the high-band mode, the PA achieves a maximum PAE of 38.4&#x0025;, a power gain of 18.1 dB with an output power of 30.1 dBm. The chip area of the proposed reconfigurable PA is 2 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 mm² including all RF and dc pads.

A SiGe BiCMOS Amplifier-Frequency Doubler Chain Operating for 284–328 GHz

This work describes the development of an amplifier frequency doubler chain (AFDC) operating at around 300 GHz based on SiGe BiCMOS technology. The driver amplifier is based on the differential cascode configuration, which employs coupled-line transformers for compact design. The frequency doubler is based on the class-B topology, which is known for exhibiting a large output power with low DC power consumption. The integrated AFDC, which consists of the frequency doubler and the preceding driver amplifier, exhibited a measured peak output power and DC-to-RF efficiency of -0.9 dBm and 0.97%, respectively, along with a conversion gain of -0.1 dB. It operates from 284 to 328 GHz with a 0-dBm input signal, consuming a total DC power of only 84 mW. The chip size is 720 × 310 μm2, excluding RF and DC pads.

A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process

This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

High-Isolation Multimode Multifunction 24-/60-GHz CMOS Dual-Bandpass Filtering T/R Switch

Fully integrated 24-/60-GHz dual-band transmit/receive (T/R) switch capable of bandpass filtering and switching operations in single bands and concurrent dual band, coupled with simultaneous transmission and reception, is developed using a 0.18- $\mu \text{m}$ SiGe BiCMOS process. The developed bandpass filtering switch can also function as a diplexer with switching functions. The measured insertion losses of the T/R switch are 2.9 and 8.7 dB at 24 and 60 GHz in single-band modes and 3/8.8 dB at 24/60 GHz in concurrent dual-band mode, respectively. The measured isolations are 53 and 43 dB at 24 and 60 GHz in single-band modes and 50/57 dB at 24/60 GHz in concurrent dual-band mode, respectively. The measured inputs $P_{1-\text {dB}}$ are 20.6 and 16.4 dBm at 24 and 60 GHz in single-band modes and 15.9/13 dBm at 24/60 GHz in concurrent dual-band mode, respectively. The measured inputs IP3 are 23.2 and 22.5 dBm at 24 and 60 GHz in corresponding single-band modes, respectively. The total chip size is $1480~\mu \text{m}\times 520~\mu \text{m}$ excluding all the RF and dc pads.

90 GHz CMOS Phased-Array Transmitter Integrated on LTCC

This paper presents the design of a 90 GHz phased-array transmitter front end on low-temperature co-fired ceramic (LTCC) technology. The monolithic microwave integrated circuit components have been fabricated by the CMOS technology and flip chipped on the LTCC to realize the transmitter front end. The dc and differential hybrid IF signals are provided to the flip-chipped components through the bias and IF lines designed on the LTCC. An $1 \times 4$ patch antenna array has been designed for the transmitter and fabricated on the LTCC. The dc and IF signal pads on the LTCC were soldered to the designed printed circuit board pads for measurements. The measurement results show that by using a receiver horn antenna, the maximum received power at 92 GHz is −37.3 dBm at a communication distance of 1 m. The transmitter is capable of providing ±25° beam steering with respect to boresight and 20° half-power beamwidth at 90 GHz. The total power consumption of the transmitter front end is 656 mW.

A D-Band Integrated Signal Source Based on SiGe 0.18μm BiCMOS Technology

This work describes the development of a D-band (110?170 GHz) signal source based on a SiGe BiCMOS technology. This D-band signal source consists of a V-band (50?75 GHz) oscillator, a V-band amplifier, and a D-band frequency doubler. The V-band signal from the oscillator is amplified for power boost, and then the frequency is doubled for D-band signal generation. The V-band oscillator showed an output power of 2.7 dBm at 67.3 GHz. Including a buffer stage, it had a DC power consumption of 145 mW. The peak gain of the V-band amplifier was 10.9 dB, which was achieved at 64.0 GHz and consumed 110 mW of DC power. The active frequency doubler consumed 60 mW for D-band signal generation. The integrated D-band source exhibited a measured output oscillation frequency of 133.2 GHz with an output power of 3.1 dBm and a phase noise of -107.2 dBc/Hz at 10 MHz offset. The chip size is 900 × 1,890 μm², including RF and DC pads.

Submillimeter‐wave InPHBT power amplifier using impedance‐transforming two‐way balun

ABSTRACTIn this letter, a submillimeter‐wave power amplifier (PA) is presented using a 250 nm InP HBT technology. To obtain high output power, a two‐way power combiner with differential outputs is proposed using multimetal layers. This two‐way balun has an embedded impedance‐transformation function, which enables to design broadband and low‐loss impedance matching networks of a PA. The back‐to‐back connected balun shows a measured insertion loss of 1.2 dB at 296 GHz, including the losses of RF pads. The balanced PA using cascode power cells and the baluns exhibits a measured small‐signal gain of 9.0 dB with broad bandwidth, and the measured output power of 10.0 dBm with a gain of 6.0 dB and drain efficiency of 5.4% at 296 GHz. The chip size is as small as 0.49 mm × 0.41 mm including DC and RF pads. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1831–1834, 2015

A broadband, high isolation millimeter-wave CMOS power amplifier using a transformer and transmission line matching topology

This paper presents the design and characterization of a broadband millimeter-wave PA realized in a 130 nm standard RF-CMOS process with 8-metal-layer and transistor f T /f MAX of 117/161 GHz. The power amplifier adopts transformer and transmission line matching topology which achieves small area of die and wide bandwidth. A new lumped transformer model is proposed to facilitate the optimization. The measured 3 dB bandwidth is 20 GHz (from 47 to 67 GHz), the measured maximum gain is about 8.6 dB, output 1 dB compression power is 9.36 dBm and consumes 90 mA current from DC supply 1.2 V. Including GSG and DC pads, the PA occupies a compact chip area of 0.318 mm2, and without pads, the PA occupies 0.141 mm2.

HIGH PERFORMANCES LOCAL OSCILLATOR SIGNAL DRIVER FOR 60 GHZ I\Q SYSTEMS IN 65NM CMOS TECHNOLOGY

This paper shows the design of a reduced size system that drives local oscillator (LO) signal generated by a voltage controlled oscillator (VCO) in the transceiver system, which is based on I and Q architecture. The aim of this work is to obtain a small system capable to drive two difierential mixers and one phase locked loop block with high power e-ciency. The entire system drives two difierential outputs to their respective mixers with a minimum difierential LO power of i1dBm and a maximum of 0dBm between 56.5 and 60GHz. The system furnishes i7dBm to the PLL, allowing the control of the carrier. The output ports are matched at 50› and they achieve a re∞ection loss under 10dB in the whole band of interest. The power consumption of the entire system is 58mW. The size including RF and DC pads is 0:6 £ 0:7mm 2 .

A 90-nm CMOS 144 GHz Injection Locked Frequency Divider with Inductive Feedback

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90- nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm × 0.69 mm including the DC and RF pads.

A miniature low-power ultra-wideband low noise amplifier in 0.18 μm CMOS

A 0.18-μm CMOS low-noise amplifier (LNA) operating over the entire ultra-wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of −8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from −8 to −1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm2 without RF and DC pads. The design uses only two on-chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.

A Two-Channel 8–20-GHz SiGe BiCMOS Receiver With Selectable IFs for Multibeam Phased-Array Digital Beamforming Applications

An 8-20-GHz two-channel SiGe BiCMOS receiver is presented for digital beam-forming applications. The receiver is based on a dual-down-conversion architecture with selectable IF for interference mitigation and results in a channel gain (in-phase and quadrature paths) of 46-47 dB at 11-15 GHz and >;36 dB at 8-20 GHz with an instantaneous bandwidth of 150 MHz. A 2-bit gain control (0-16 dB) is also provided at baseband. The mea sured noise figure (NF) is <;4.1 dB (3.1 dB at 15-16 GHz) and is independent of the gain state. The measured OPldB is -10 dBm and the input PldB is -56 to -40 dBm at 15 GHz depending on the gain, which is sufficient for satellite applications. The on-chip channel-to-channel coupling is <; -48 dB. The measured evanescent mode is <;3% for a 1-Ms/s quadrature phase-shift keying (QPSK) modulation at 8-20 GHz, and <;1.8% for a 0.1-, 1-, and 10-Ms/s QPSK, 16 quadrature amplitude modulation (QAM), and 64-QAM modulations at 15 GHz. The chip is fabricated using a 0.18-μm SiGe BiCMOS process, has electrostatic discharge protection on the RF and dc pads, consumes 70 mA per channel from a 3.0-V power supply, and is 2.6 × 2.2 mm2, including all pads. A 15-GHz eight-element phased array with an NF <;3.8 dB is also demonstrated with multiple simultaneous beam performance. To our knowledge, this is the first two-channel 8-20-GHz beam-forming chip in SiGe BiCMOS technology.

A multiband carrier generation architecture for UHF, 2.4 GHz, and 5 GHz ISM applications

Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a-b-g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross-coupled LC VCOs to generate in-phase (I) and quadrature (Q) signals operating at one-thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single-stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is −104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm2 on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.

Design of a tunable multi-band differential LC VCO using 0.35 μm SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2–5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3V for 5 different frequency bands (2.27–2.51GHz, 2.48–2.78GHz, 3.22–3.53GHz, 3.48–3.91GHz and 4.528–5.7GHz) with a maximum bandwidth of 1.36GHz and a minimum bandwidth of 300MHz. The designed and simulated VCO can generate a differential output power between 0.992 and −6.087dBm with an average power consumption of 44.21mW including the buffers. The average second and third harmonics level were obtained as −37.21 and −47.6dBm, respectively. The phase noise between −110.45 and −122.5dBc/Hz, that was simulated at 1MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between −176.48 and −181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76GHz without FOM and area abandonment. Output power of the fundamental frequency changes between −6.087 and 0.992dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4–6.3mA and between 11.4 and 15.3mA with the buffer circuit from 3.3V supply. The circuit occupies an area of 1.477mm2 on Si substrate, including DC, digital and RF pads.

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, −Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is −110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and −113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm2 on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.