DC Offset Suppression Research Articles

W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication

This article presents a pair of W-band phased-array transmitter (TX) and receiver (RX) chipsets in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS process for high data-rate wireless communication. Both the chips integrate four compact front-end channels in 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 distribution, and the distance between the adjacent RF pads is less than 1.8 mm ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.56\lambda $ </tex-math></inline-formula> at 90 GHz) to fit for the tight antenna array and enable array scaling by tiling multiple unit cells. A 6-bit active phase shifter based on the improved phase-inverting variable gain amplifiers is leveraged to achieve high phase-shift precision and bandwidth concurrently. A noise reduction technique using a parallel inductor to resonate with the parasitic capacitors of the cascode transistors is adopted in the low-noise amplifier design. A novel miniature power combiner, which occupies a much more compact area than the Wilkinson power combiner while delivering great RF performance, is proposed and elaborately analyzed. System-level calibration for local oscillator (LO) leakage and dc-offset suppression is enabled by introducing digitally controlled current sources into the up-conversion and down-conversion mixers. On-wafer measurements for the TX chip exhibit a single-channel IF-to-RF conversion gain (CG) of 26 dB, a competitively high output 1-dB compression point (OP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) of 11 dBm. The RX chip achieves an RF-to-IF CG of 19.5 dB with 9-/14-GHz IF/RF 3-dB bandwidth, a noise figure of 7.7 dB, and an input 1-dB compression point of −28 dBm. The phase-shift characteristics are verified by the TX/RX front-end measurements, achieving a 6-bit phase resolution with minimum rms phase/gain error smaller than 0.83°/0.45 dB and a large phase-shift bandwidth higher than 20 GHz. Preliminary wireless transmission test using a low-cost die-on-printed circuit board (PCB) prototype demonstrates wireless data rates of 1.6 and 0.8 gigabits per second (Gb/s) at distances of 0.4 and 1 m with 256-quadratic-amplitude modulation (QAM) and 16-QAM modulated signals, respectively.

A unipolar thin‐film transistor‐based amplifier with enhanced DC offset suppression

This letter proposes a unipolar thin-film transistor (TFT)-based amplifier design that can provide enhanced DC offset suppression. The amplifier consists of an input AC coupling network and a capacitor bootstrap amplifier. By making the first pole of the input AC-coupling network coincide with that of the capacitor bootstrap amplifier, a DC offset suppression capability of 40 dB/dec, which is 2× higher than that of the prior arts, can be obtained. An implementation is also proposed and a Rensselaer Polytechnic Institute (RPI) TFT model whose parameters are turned to fit the measured data of our metal-oxide TFT is used to simulate the circuit. Simulation results show that the implementation has 31 dB midband gain, 0.5 Hz–5 kHz bandwidth, 300 μW power consumptions, and the expected 40 dB/dec DC offset suppression. This design is suitable for applications that need to block large DC interference, such as sensor readout amplifiers.

Morphological Fault Detector for Adaptive Overcurrent Protection in Distribution Networks With Increasing Photovoltaic Penetration

In this paper, a versatile and robust algorithm for overcurrent protection that is adaptive to the feeder PV penetration level as well as changing load condition in the distribution feeder is proposed. The algorithm has built-in dc-offset suppression capability as well as recursive least square error filter for current phasor estimation to provide input to the overcurrent fault detector. The proposed multistage morphological fault detector analyzes sudden change in fault current magnitude and its structure makes it convenient to update the fault threshold dynamically by measuring the current magnitude at regular interval, thus making the algorithm versatile and adaptive. The performance of the proposed algorithm is investigated by simulating different fault distances and fault types for increasing penetration levels of PVs on a simple radial distribution feeder .

A $64.8~\mu$ W &gt; 2.2 G $\Omega$ DC–AC Configurable CMOS Front-End IC for Wearable ECG Monitoring

This paper presents a low-power and high input impedance dc–ac configurable CMOS front-end integrated circuit (IC) for wearable ECG monitoring. This IC mainly includes three parts, namely: 1) high input impedance dc-coupled instrumentation amplifier; 2) AC-coupled programmable gain amplifier; and 3) low-power single operational amplifier continuous-time $\Sigma \Delta $ modulator. In addition, on-chip power management and clock generator were implemented to minimize the device size of the ECG monitoring system. This IC can be configured to dc-coupled topology to achieve ultra-high input impedance for dry electrode, and ac-coupled topology to achieve better electrode dc offset suppression for wet electrode. A baseline wander tracking technique is proposed to eliminate baseline disturbance, and a right-leg-driven circuit is realized to enhance the common-mode rejection ratio and minimize the 50/60 Hz power line interference. Fabricated in 0.18- $\mu \text{m}$ CMOS process, this front-end IC occupies 0.24 mm2 active area and consumes 64.8 $\mu \text{W}$ from a 1.8-V supply. It achieves peak SNR 54.7 dB, spurious free dynamic range 58.2 dB, input impedance higher than 2.2 $\text{G}\Omega $ , and dc suppression as large as ±300 mV.

BER performance analysis of a direct conversion receiver

Direct conversion receivers are increasingly popular for use in mobile terminals. This is due to advantages over other architectures such as heterodyne receivers in terms of cost, electrical current, and physical size. However, a direct conversion receiver often generates a DC-offset that has to be taken care of either by suppressing the DC-offset in the radio-frequency part of the receiver, or by taking care of it during baseband processing. A theoretical analysis of the bit error rate (BER) performance in a direct conversion receiver with different levels of DC-offset suppression is presented. Explicit results are presented on how the BER depends on the signal-to-noise ratio (SNR), the signal-to-DC-level, and the choice of pilot symbols both with M-QAM and M-PSK in a slow, flat Rayleigh fading channel. A design rule, which applies to the design of DC-compensation in direct conversion receivers, is also presented.