Dc-link Voltage Ratio Research Articles

Model Predictive Power Control of Grid-Connected Quasi Single-Stage Converters for High-Efficiency Low-Voltage ESS Integration

The grid-connected quasi-single-stage converter (QSSC) provides a direct power flow path from low-voltage (LV) energy storage systems (ESS) to ac–dc converters, resulting in reduced power conversion stage for high-efficiency ESS integration. However, due to the dc-link voltage ratio between the two ports varies with the ESS state of charge, the voltage vectors in the ac side are unevenly distributed in the QSSC. This nonlinearity brings some challenges in control and modulation design for the ac–dc part of QSSC. In this article, a virtual two-level converter model considering the two ports as a single dc source is proposed, and model predictive power control (MPPC) based on the virtual two-level model is proposed to enhance the grid current performance. The duty cycle of each phase is calculated based on the active and reactive power tracking error minimization in the two-level converter frame, and the duty cycle for each switching pair is obtained by minimizing the power processed by the dc–dc converter. In this way, the complicated implementation of MPPC for a three-level converter is avoided, and the controller design of the QSSC can be simplified. The effectiveness of the proposed virtual two-level converter model and MPPC method are verified with experimental results.

An Enhanced SVPWM Strategy Based on Vector Space Decomposition for Dual Three-Phase Machines Fed by Two DC-Source VSIs

This article presents an enhanced space vector pulse width modulation (SVPWM) strategy based on vector space decomposition (VSD) for the dual three-phase machines fed by two dc-source voltage source inverters (VSIs). Compared with existing methods that only account for balanced dc-link voltages, the proposed method considers unbalanced dc-link voltages in both the α-β and z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> planes. Two categories of medium voltage vectors are first defined in this article. An enhanced 12-sector SVPWM strategy that toggles two categories of medium voltage vectors in each fixed 30° sector is proposed. Moreover, the performance of the proposed method, including the modulation depth, the range of the dc-link voltage ratio, and the toggling point of the medium vector is analyzed. The proposed method can reduce the computational burden of the complicated sector classifications and it easily chooses suitable vectors to track the reference voltage with changes in the dc-link voltage ratio. The experimental results of the proposed SVPWM techniques are verified in a dual three-phase permanent magnet synchronous machine (PMSM) fed by two dc-source VSIs.

A Universal Lookup Table-Based Direct Torque Control for OW-PMSM Drives

For open-winding permanent magnet synchronous motor (OW-PMSM) system with two isolated dc voltage sources, the distribution of voltage vectors (VVs) is different under different dc-link voltage ratios. In this letter, a universal lookup table (LUT) based direct torque control (DTC) strategy is proposed for OW-PMSM drives under different conditions of the dc-link voltage ratio. The distribution criterion of VVs under various dc-link voltage ratios is analyzed and the VVs are assigned to different regions by designing a generalized region division scheme. A universal LUT is established to realize the selection of required VV in the DTC strategy. Experimental results validate the effectiveness of the proposed universal LUT-based DTC strategy for the OW-PMSM system with different voltage ratios.

Capacitor Voltage Balancing for Single-Phase Asymmetric Cascaded H-Bridge Inverters

This article presents an analysis of conventional single-phase cascaded H-bridge multilevel inverters composed of two and three cells. The dc-link can be a dc source or a floating capacitor. Two methods are given to regulate the floating capacitor voltage. In this way, according to the capacitor voltage balancing method used, operating regions and power distribution on the floating capacitor are presented for different dc-link voltage ratios and several ranges of modulation index and load power factor. A mathematical analysis is done in order to demonstrate the influence of the modulation index and load power factor over the power distribution. Finally, simulation and experimental results are provided to validate the theoretical considerations.

A New Variable Frequency Control of 49-Level Cascaded Packed U-Cell Voltage Source Inverter

Requirement of large number of levels with lower number of switching devices has made asymmetrical converters more popular than the symmetrical ones. Asymmetrical cascaded multilevel inverters (ACMLI) can achieve high efficiency by combining switching devices with different voltage ratings and technologies. The proposed ACMLI cascades two or more units of packed U-Cell (PUC) inverters using two or more isolated dc link supplies. In this article, one of the PUC unit is controlled using high switching frequency while the other PUCs are operated in a step mode at low switching frequencies, thus operating them in a variable frequency control mode. The cascading of two 7-level PUC inverters with dc link voltage ratio of 1:7 can produce an output voltage with 49 (7x7) levels. The multilevel output voltage waveform is nearly sinusoidal with very low THD content, and the low switching frequency operation leads to lower power dissipation and greater system efficiency. However, each PUC module requires two dc voltage sources. To address this concern, in this article, each PUC module consists of one dc voltage source and one dc bus capacitor. With the cascaded PUC topology and proposed control algorithm, load current and dc bus capacitor voltage control is achieved simultaneously. The proposed converter and its control technique lead to the breaking of the design tradeoff rule between switching frequency (efficiency) and filter size. This is very useful in various applications such as uninterruptible power supplies and grid-tie inverters. The converter and its control technique are simulated using MATLAB/Simulink software and simulation results for both open loop and closed loop are discussed. Hardware results are obtained by developing a 1-kW experimental prototype. Simulation and experimental results confirm the usefulness and effectiveness of the proposed topology and its control technique.

Dc‐link voltage stability analysis technique for hybrid five‐phase open‐end winding drives

The dc-link voltage stability for a hybrid five-phase open-end winding (OeW) drive operating under carrier-based pulse-width modulation is studied. The drive consists of a five-phase induction machine, supplied using one three-level and one two-level voltage source inverter. This configuration is analysed for the case of isolated dc-link rails, while the dc-link voltage ratio is considered as an additional degree of freedom. It is demonstrated that different dc-link voltage ratios lead to the different overall number of voltage levels across stator windings. Modulation strategies are investigated and their performances are analysed from the dc-link voltages stability point of view. An analytical method for dc-link voltage stability analysis is presented. Results show that the four-level configuration always leads to stable dc-link voltages, regardless of the modulation strategy. On the other hand, if the six-level configuration is combined with modulation strategies that lead to optimal harmonic performance, not all dc-link capacitor voltages will be in the balance depending on the operating conditions.

Control of asymmetrical cascaded multilevel inverter for a grid‐connected photovoltaic system

This article presents a generalised asymmetrical cascaded multilevel inverter (MLI) for a single-phase grid-connected photovoltaic (PV) system and their control strategy. The control strategy, including maximum power tracking along with a suitable interface, is implemented for maximum power transfer from the PV source to the single-phase low-power grid. The balancing of DC-link voltages for an asymmetrical MLI under variable solar parameters as well as grid parameter variation is implemented using the proposed control strategy. The voltage controllers maintain the constant DC-link voltage ratio, whereas the current controller injects the sinusoidal current into the grid at unity power factor and track the grid voltage under variation of grid voltage using grid tracker. Stability analysis of the proposed grid-connected asymmetrical inverter system is also incorporated. The whole grid-tied PV system is simulated in the MATLAB/SIMULINK environment and the exhaustive simulation results of the system under different transient conditions are presented. In addition, a laboratory prototype for a low-power grid-tied PV system has been developed and implemented using DS1103. The performance of the system is also tested at varying irradiance conditions and the corresponding experimental results are also presented.

Performance analysis of cascaded h-bridge multilevel inverter using mixed switching frequency with various dc-link voltages

Multilevel inverters have been widely used in many applications since the technology is advantageous to increase the converter capability as well as to improve the output voltage quality. According to the applied switching frequency, multilevel modulations can be subdivided into three classes, i.e: fundamental switching frequency, high switching frequency and mixed switching frequency. This paper investigates the performance of cascaded H-bridge (CHB) multilevel inverter that is modulated using mixed switching frequency (MSF) PWM with various dc-link voltage ratios. The simulation results show the nearly sinusoidal load output voltages are successfully achieved. It is revealed that there is improvement in output voltages quality in terms of THD and low-order harmonics content. The CHB inverter that is modulated using MSF PWM with equal dc-link voltage ratio (½ Vdc: ½ Vdc) produces output voltage with the lowest low-order harmonics (less than 1% of fundamental) while the CHB inverter that is modulated using MSF PWM with un-equal dc-link voltage ratio (2/3 Vdc: 1/3 Vdc) produces a 7-level output voltage with the lowest THD (16.31%) compared to the other PWM methods. Improvement of the output voltage quality here is also in line with improvement of the number of available levels provided in the output voltage. Here only 2 cells H-bridge inverter (contain 8 switches) are needed to produce a 7- level output voltage, while in the conventional CHB inverter at least 3 cells of H-bridge inverter (contain 12 switches) are needed to produce a 7-level output voltage. Hence it is valuable in term of saving number of component.

Optimization of Harmonics for Cascaded Multilevel Inverter with Variable DC SourceVoltages Using Mutative Methods

A new approach of Harmonic Optimization of a single phase 5-level Cascaded Inverter using Selective Harmonic Elimination (SHE) is proposed in this paper. Here the DC Source voltages are considered as time varying and hence a term DC link voltage ratio is taken into account in this regard. The switching angles and DC link voltage ratio are computed using Genetic Algorithm and Particle Swarm Optimization through solving the non-linear transcendental equations describing the SHE problem that would result in minimized Total Harmonic Distortion (THD) of the output voltage waveform. Two distinct approaches: firstly, elimination of lower order Harmonic (3rd) with maintaining a desired fundamental output voltage and secondly, reducing a number of lower order harmonics (3rd, 5th, 7th, 9th, & 11th) with maintaining the fundamental output voltage are considered in this paper to minimize the Total Harmonic Distortion (THD) with giving consideration to the switching angles and the DC link voltage ratio as the optimization variables. The %THD (considering all harmonics up to 49th) of the output voltage waveform is calculated using the switching angles and DC link voltage ratio for different modulation indices. The whole procedure is repeated for equal DC source voltages and the corresponding results are compared. The switching angles, DC link Voltage ratios, and %THD obtained from the offline computation are stored in a direct look up table which can be easily applied to the online control for real time application. Simulation is being done to demonstrate the analytical results.

Asymmetrical Cascaded Multilevel Inverter Based on Transistor-Clamped H-Bridge Power Cell

This paper presents an asymmetrical cascaded multilevel inverter based on a five-level transistor-clamped H-bridge power cell. A two-cell configuration with a dc link voltage ratio of 4 : 1 is presented. The modulation method is based on the fundamental frequency switching. An analysis of the inverter output voltage and harmonics is presented. Injection of the third harmonic voltage as to maximize the output voltage and the issue of the inverse power flow or regeneration in the low-voltage cell are presented. The prototype of the proposed inverter was built, and its functionality was verified through experimental results.

Cascaded two-level inverter-based multilevel static VAr compensator using 12-sided polygonal voltage space vector modulation

A static VAr compensation scheme using 12-sided polygonal voltage space vectors for high power application is proposed in this study. Using the polygonal voltage space vectors, the dc bus utilisation is increased in linear modulation region and total harmonic distortion (THD) is improved significantly in over modulation region. The power circuit topology consists of two standard two-level inverters, which are connected in cascade through an open-ended winding transformer. In order to obtain the polygonal voltage space vectors, the dc-link voltage of inverter 2 is maintained at 0.366 times the dc-link voltage of inverter 1. A simple control strategy to maintain the required dc-link voltage ratio as well as for reactive power compensation is proposed. To verify the proposed strategy, simulation is carried in MATLAB/SIMULINK. Simulation study is performed in linear, over modulation regions of the inverter and also with unbalanced network voltages. A laboratory prototype is designed and developed to validate the simulation results. Further, this scheme is compared with a sinusoidal pulse width modulation-based VAr compensation scheme using the same topology.

Compensation of Nonlinearities in Diode-Clamped Multilevel Converters

The application of multilevel converters for exciting permanent-magnet machines with low-phase inductance to dc-link voltage ratios facilitates a reduction in high-frequency switching harmonics. However, converter nonlinearities and, in-particular, on-state device voltage drops, create additional low-frequency harmonics. This paper therefore proposes a generic compensation scheme to accommodate the effects of such converter nonlinearities and, in doing so, improve the harmonic quality of the machine phase currents. Experimental results gathered from a prototype five-level diode-clamped converter validate the benefits of the proposed scheme by showing quantitative reductions in low-frequency harmonics.