DC-link Capacitor Voltage Research Articles

Modified PDPWM control with MPPT algorithm for equal power sharing in cascaded multilevel inverter for standalone PV system under partial shading

<span lang="EN-US">In this paper, a modified particle swarm optimization (MPSO) based maximum power point tracking (MPPT) controller is used to track the maximum power of a PV system using DC-DC boost converter technology. </span><span lang="EN-GB">To raise the PV module's input DC voltage, a DC-DC boost converter was employed. The boost converter powered the DC-AC multilevel PWM inverter, which then delivered the output AC voltage to a solitary inductive load. Cascaded multilevel inverters are often used to condition power in renewable energy applications because they are easy to use and have few parts. Ripples in the voltage of DC link capacitors cause low order harmonics and inter harmonics in the multilevel inverter's output voltage. Phase disposition pulse width modulation (PDPWM) has the fewest harmonics. The inverter cells' power delivery is not equal in this manner. In the present paper, a strategy for improving sharing of power PDPWM for photovoltaic applications is proposed. The modified PDPWM is used on a 9-level inverter where each cell is connected to a PV array running at maximum power point tracking MPPT and under partial shadowing for single phase multilevel inverters. The MATLAB/SIMULINK software was used to do simulations, and the findings demonstrate that the method presented is effective at balancing the way power is shared between different inverter cells and reducing the voltage ripple of the DC link capacitor.</span>

Comprehensive Analysis and Evaluation of DC-Link Voltage and Current Ripples in Symmetric and Asymmetric Two-Level Six-Phase Voltage Source Inverters

Multiphase drives (MPD) in general and six-phase in particular have been gaining popularity in many industries, which calls for a proper multiphase inverter (MPI) design. For voltage source inverter (VSI)-fed drives, the knowledge of voltage and current stresses on the dc-link are imperative for input capacitor sizing. To this end, the voltage and current stresses on the dc-link capacitor in two-level six-phase VSIs are examined thoroughly in this article for two configurations of load/winding spatial distribution: symmetric and asymmetric. First, the harmonic spectrum of the input dc current of each inverter is analyzed in detail by benchmarking them against the conventional three-phase VSI, to precisely establish the dc-capacitor requirement reduction in six-phase counterparts. Second, analytical formulae for the dc-link capacitor voltage ripples are derived for both configurations. Third, simple formulae for dc-capacitor sizing for six-phase VSIs with different load configurations are provided. The accuracy of the derived formulae is verified by simulation and experimental testing at various power factors and modulation depth. It is found that six-phase VSI supplying symmetric and asymmetric loads reaps 10% and 7% lower dc-link current ripples, respectively. Hence, six-phase symmetric loads yield the smallest capacitor size.

A Three-Phase Dual-Output T-Type Three-Level Converter

A novel three-phase dual-output T-type three-level converter (DO-T-TLC) topology is proposed in this article. The proposed topology has the dc-link and two sets of three-phase ac voltage output terminals. The topology of DO-T-TLC is introduced. Then, the operating principle of multiplexing switches and the available switching states of converter are analyzed, including current path, output phase voltage level, and blocking voltage of different switching states. The phase disposition pulsewidth modulation scheme with dc offsets is discussed in detail, and the key problems of the modulation scheme under both the common frequency and different frequency operation modes, such as voltage level selection, displacement angle constraint, and modulation index range, are studied. For the imbalance of two series capacitors in the dc-link, the mechanism is first revealed, and then a dc-link capacitor voltage balance method to control the average neutral point current is proposed. When DO-T-TLC is used in different operation modes, the ability and effect of this method to balance capacitor voltages are summarized. A low-power three-phase prototype is built, and the experimental results are given to verify the feasibility of the proposed topology and the effectiveness of the modulation scheme to control the voltage balance.

Balancing control scheme of DC-link capacitor voltages for five-level hybrid T-type inverters without auxiliary circuit

Balancing control scheme of DC-link capacitor voltages for five-level hybrid T-type inverters without auxiliary circuit

A Seven-Level Inverter With Natural Balance and Boosting Capability

This paper introduces a new active-neutral-point clamped (ANPC) seven-level inverter with a switched-capacitor technique. The introduced inverter generates a seven-level ac output voltage with a maximum voltage-boosting gain of 1.5. The higher output voltage does not imply high voltage across the switches, as the maximum blocking voltage of the switches does not exceed the input voltage. The dc-link capacitor voltages are naturally balanced, and the flying capacitor achieves self-balancing through the series-parallel connection of the input voltage source, without the need for auxiliary control methods. Additionally, compared to major traditional seven-level inverters such as NPC, FC, and hybrid topologies, the proposed topology reduces the dc voltage requirement by 33.3%, eliminating the need for an intermediate dc-boosting stage and making the introduced inverter a good candidate for applications such as photovoltaic panels and full-cells systems, both characterized by a low input voltage. The operation and performance of the proposed topology are validated through simulation and experimental results.

Single Phase Harmonic Mitigation Using Particle Swarm Optimization in Shunt Adaptive Power Filter

Purpose – These load sources are the main cause of generating harmonics, generating power loss in the transmission system and electrical equipment system, as well as reducing the life of electrical equipment, reducing the accuracy of electrical measuring devices, and reducing the signal transmission of communication devices. Methodology/Approach – This study applies the Particle swarm optimization (PSO) algorithm to DC-link capacitor voltage control based on the Proportional-integral (PI) control algorithm to determine the reference current. MATLAB/Simulation 2019a is used to simulate research results. Findings – The harmonic compensation performance of the SAPF circuit gives good results and meets the standard for total harmonic distortion (THD) of less than 5%. Originality/Value of paper – Bridge rectifiers with RL load and Non-linear load with active RC are applied in a single-phase power supply. The single-phase voltage source inverter is used to shunt the adaptive power filter (SAPF) to compensate for reactive power and current harmonics.

Advanced Vector Controller for a Four-Switch Three-Phase Rectifier under Unbalanced Grid Voltage

One of the main challenges of a four-switch three-phase rectifier (FSTPR) is a DC imbalance in capacitor voltages. On the other hand, under unbalanced grid voltage conditions, unbalanced three-phase input current and the DC-link voltage affect the performance of the FSTPR. Although many papers focus on designing a controller to balance DC-link capacitor voltage, a few papers are available to cope with the imbalance of DC-link capacitor voltages and input current simultaneously under unbalanced grid voltage. In this paper, first, the operation of the FSTPR under unbalanced grid voltage conditions is investigated. It can be seen that under these conditions, the oscillatory parts of the active and reactive input power, i.e., sin and cos components, are the leading cause of the problems that can severely degrade the FSTPR performance of the controller. Therefore, this paper presents a promising control technique to eliminate the mentioned oscillation components. Aiming at this purpose, the current control loops in the dq axis are divided into two positive and negative sequences, i.e., idq+ and idq−. Simulation results in MATLAB/SimPowerSystem™ show that the proposed controller can reduce the output voltage ripple, the total harmonic distortion, and the unbalancing of input current compared to a conventional controller. Under these conditions, the DC-link capacitor voltages are more balanced, significantly reducing the voltage limiter of the FSTPR.

A Self-Voltage Balanced Hybrid Three-Level MV Inverter Using 3.3-kV SiC MOSFET Module With False-Trigger-Proof Design

This article presents a self-voltage balanced three-level (3L) active-neutral-point-clamped (ANPC) medium-voltage (MV) inverter. Two switches of this inverter operate at high frequency (HF), while four switches operate at low frequency (LF), which is suitable to be implemented with hybrid “Si IGBTs + SiC MOSFETs” for MV applications. A 3.3-kV SiC MOSFET power module with low parasitic packaging is applied as HF switches, and the dc-link capacitor voltages can be self-balanced through periodic charging/discharging processes with a small decoupling capacitor. However, the inrush current occurs during voltage balancing processes, resulting in the false trigger of desat protection for LF switches. In this article, the mechanism of inrush current during voltage balancing processes is analyzed and a 3L gate driving method is proposed for LF switches to solve the false-triggering issue and improve the inrush energy loss distribution. In addition, high dv/dt of SiC switching transients may cause the false-triggering issue of HF switches, and desat protection design equations are therefore derived for this 3.3-kV SiC MOSFET power module to achieve a fast (< 440 ns) short-circuit response and maintain a good noise immunity to high dv/dt. A 4-kV dc, 40-kVA inverter prototype is built in the laboratory and the experimental results are provided to verify the proposed methods.

A Novel Voltage-Boosting Modulation Strategy to Reduce DC-Link Capacitance for Brushless DC Motor Drives

In this article, a novel method is proposed to reduce the dc-link capacitance of the brushless dc motor (BLDCM) system. In the proposed strategy, the charging mode of dc-link capacitor is designed to improve the energy stored by dc-link capacitor in the charging process instead of reducing the discharge time of dc-link capacitor used in previous article. The new modulation strategy and controller is designed to pump the dc-link capacitor voltage and ensure that it exceeds the ac voltage peak. The proposed modulation strategy has three vectors. The charging vector is used to improve the dc-link capacitor voltage, and the effective vector and zero vector are used to adjust the motor speed. For practical application, we provide an engineering calculation method to get the dc-link capacitance, and prove that the dc-link voltage can exceed the average voltage of the BLDCM. The experimental results verify the correctness of the theoretical analysis and the feasibility of the proposed method.

An Adaptive DC-Link Voltage Control of a Multifunctional SPV Grid-Connected VSI for Switching Loss Reduction

In the proposed method in this article, to minimize the burden on the switches of the multifunctional grid-connected voltage-source inverter (MFGCVSI), the voltages of dc-link split capacitors are adjusted according to power injection from the MFGCVSI. The MFGCVSI is used to control the active power injection from solar photovoltaic (SPV) power generation to the main grid and loads, load reactive power compensation, harmonic mitigation, and main grid current total harmonic distortion within 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> . In such a case, the voltages of split capacitors depend on the rated power injection from the MFGCVSI. The power generated from the SPV system and the loads that are connected at the point of common coupling vary with respect to time. It is observed that the selection of rated dc-link voltages during low power injection from the MFGCVSI leads to additional switching stress and higher switching losses. Therefore, to reduce the burden on inverter switches and switching losses, the reference dc voltage is reduced under low power injection from the MFGCVSI. A model predictive controller with a multiconstraint technique is used in the proposed method for balancing the dc-link capacitor voltages and average switching frequency reduction. The proposed method is validated through simulation and hardware setup.

Reduced Capacitor Energy Requirements in Battery Energy Storage Systems Based on Modular Multilevel Converters

Battery energy storage systems (BESS) based on modular multilevel converters (MMCs) allow battery packs to be integrated into the electrical grid in a modular fashion. Inherent to the operation of the MMC, the module's dc-link capacitor voltage experiences oscillations at grid frequency and its harmonics. This article investigates the close relation between this voltage oscillation and the battery current ripple. The precise capacitor energy requirements for various operations of BESS-MMC, which include arm/phase power balancing and state-of-charge balancing are analyzed in this article. Furthermore, this article also explores the relation between the controller design and the submodule's (SMs) capacitor sizing in terms of its energy requirements. Design guidelines for the SM level voltage control to attenuate battery ripple and detailed analysis for the capacitor energy requirement in each operating mode are presented. The control and capacitor sizing design are validated in real-time using embedded microprocessors in a Typhoon-based controller hardware-in-the-loop environment.

A Flexible Reactive Power Injection Method for DC-Link Capacitors Voltage Balancing in Back-to-Back Multilevel Converters

The dc-link capacitor voltage drift is the key technical problem of the converters with multi-intermediate nodes. The back-to-back (BTB) configuration with voltage balancing control can achieve a certain operation range. Nevertheless, the challenge of voltage drift still remains, especially when both sides operate at high but different modulation indexes and high power factors. This article focuses on a BTB seven-level V-clamp multilevel converter (VMC). The balanced operation limits are presented, and the effect of the power factor on balancing capability is analyzed. To maintain the voltage balancing of the dc-link capacitor under different operation conditions of the load (inverter side), a reactive power injection control is proposed in this article. Suitable reactive power is injected into the rectifier according to the balancing situation. The proposed control method can actively adjust the power factor of the rectifier to provide the required balancing capability. In this way, the dc-link capacitor voltage balancing is maintained within a larger operation range. In this article, a 10-kVA laboratory prototype of BTB seven-level VMC is set up to verify the effectiveness of the proposed control.

Shunt active power filter with MSRF-PI-AHCC technique for harmonics mitigation in a hybrid energy system under load changing condition

ABSTRACT In this study, a shunt active power filter (SAPF) is used to measure the harmonics level of a hybrid power system based on solar PV (SPV) and wind system. The SAPF employs a modified synchronous reference frame technology, an adaptive hysteresis current controller method, and a conventional proportional and integral based voltage regulator for the generation of reference current. The recommended SAPF performs extremely well in suppressing harmonics under varied load and source conditions. The results show that the proposed model outperforms earlier approaches in terms of harmonic mitigation and dc-link voltage stability. It was created in MATLAB/Simulink. The SAPF can minimise harmonics of the source current from 26.74% to 1.565% and 20.25% to 1.80% for inductive and capacitive load case respectively under ideal source condition and 30.05% to 3.82% (inductive) and 25.25% to 3.56% (capacitive) under non-ideal source condition. The proposed controller also reduces the ripples from the dc-link capacitor voltage from 22 V to 8 V and 9 V under both the source condition, respectively, based on the numerical comparison of findings.

Nonlinear Control of a Two-Stage 1-MWh Grid-Connected Battery Energy Storage System by Exact Linearization via State Feedback

This paper presents modeling and nonlinear control of a two-stage 1-MWh battery energy storage system (BESS) connected to a distribution grid. The BESS is based on a cascaded H-bridge (CHB) multilevel converter offering the distribution of the batteries among multiple submodules which provides safer operation and more flexibility in the voltage design of the batteries. The main function of the BESS is to exchange active and reactive power by controlling the current of the CHB using voltage oriented control strategy. Moreover, this paper proposes a nonlinear state feedback exact linearization controller to control the bidirectional buck–boost converter in each submodule to charge/discharge the batteries and stabilize the dc-link capacitor voltage throughout the operation of the BESS. The proposed controller performance is compared with the conventional PI controller and validated through simulation results.

DC-Link Neutral Point Control for 3L-NPC Converters Utilizing Selective Harmonic Elimination–PWM

Selective harmonic elimination–pulsewidth modulation (SHE–PWM) is a modulation technique widely used to improve the efficiency and harmonic content in medium-voltage high-power converters. Among these converters, the three-level neutral-point-clamped (3L-NPC) converter is one of the most utilized topologies. However, the 3L-NPC converter requires a proper balancing of dc-link capacitor voltages. This article presents a control technique, based on pulse shifting method, to regulate the neutral point voltage when SHE-PWM is utilized. The proposed technique performs well with any power factor and it can also be directly applied to T-type converters and easily extrapolated to other multilevel topologies. The proposed method is experimentally validated in a scaled-down power converter and a full-scale medium-voltage 3L-NPC converter.

Baseline for Split DC Link Design in Three-Phase Three-Level Converters Operating with Unity Power Factor Based on Low-Frequency Partial Voltage Oscillations

The study sets a baseline for split DC link capacitance values and voltage set points in three-phase three-level AC/DC (or DC/AC) converters operating with unity power factor. In order to equalize the average values of partial DC link voltages, the controller generates a zero-sequence containing DC components only while employing neither dedicated DC link capacitance balancing hardware nor high-order zero-sequence component injection. Such a baseline is required in order to evaluate the effectiveness of different DC link capacitance reduction methods proposed in the literature. Unlike most previous works, utilizing neutral point current based on cumbersome analytical expressions to determine neutral point potential oscillations, the instantaneous power balance-based approach is employed in this paper, resulting in greatly simplified and more intuitive expressions. It is demonstrated that while the total DC link voltage is low-frequency ripple-free under unity power factor balanced AC-side operation, split DC link capacitors absorb triple-fundamental frequency power components with one-sixth load power magnitude. This yields significant opposite phase partial voltage ripples. In such a case, selection of DC link capacitances and voltage set points must take into account the expected values of AC-side phase voltage magnitude and split DC link capacitor voltage and current ratings. Simulation and experimental results validate the proposed methodology by application to a 10 kVA T-type converter prototype.

Third-order current harmonic suppression and neutral-point voltage balance control strategy for single-phase three-level NPC inverter

The imbalance of capacitor voltage on the DC side of the inverter will cause the third-order current harmonics and the device will be damaged greatly with the increase of voltage stress. The mechanism of imbalance capacitors voltage and the third-order current harmonics generated by the double frequency fluctuation are analyzed. This paper presents a feedforward capacitor differential pressure control strategy based on PR controller, which is aimed at the single-phase three-level NPC inverter and considers the cause of double modulation wave. The PR controller is used in the current loop to suppress the third-order harmonic by static-free tracking of the AC signal, and the voltage balance is realized by the feedforward DC-link capacitor voltage difference to offset the DC component of the output side. The simulation model and 1kW prototype driven by the control strategy have been established to demonstrate that the capacitor voltage of the inverter is balanced and the third-order harmonic is suppressed efficiently.

A Generalized Simplified Virtual Vector PWM to Balance the Capacitor Voltages of Multilevel Diode-Clamped Converters

This article presents a generalized simplified virtual vector pulsewidth modulation (SVVPWM) to attain the capacitor voltage balancing of multilevel diode-clamped converter (DCC) for all operational conditions, which is not possible by using conventional space vector pulsewidth modulation (PWM) and carrier-based PWM methods. Virtual vector PWM is a solution presented in the literature to sort out this issue but it becomes more complex for higher level converters. The proposed SVVPWM method is simple and easy to implement for any level converter because it converts the space vector (SV) diagram of any level converter to three-level SV diagram. The SVVPWM assures the natural voltage balancing under steady states and ideal operations. Under dynamic operations, a generalized equation that describes the influence of neutral point currents on dc-link capacitor's voltage has been derived and a general decoupled voltage balancing control for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -level DCC is presented. The proposed modulation method is implemented on five-level and seven-level DCCs to authenticate the effectiveness of decoupled voltage balancing control. Simulation and experimental results demonstrate that the proposed modulation strategy is easy to implement and effectively controls the balance of the capacitor voltages for the whole range of modulation index and load power factor.

Cascaded Transformers-Based Multilevel Inverters With NPC

The basic structure and generalization of two cascaded transformer multilevel inverters (CTMIs) are proposed in this paper. Such configurations are based on cascaded symmetrical transformers coupled to two-level (2L) legs and three-level (3L) neutral-point clamped (NPC) legs. One configuration has a shared 2L leg, connected to all transformers. The other configuration consists of multiple shared legs, where each is connected between two transformers. A modulation technique is also presented that allows only one leg of the proposed inverters operates at high frequency, while all other legs operate at low frequency. Compared to three conventional CTMIs, the proposed structures can produce more output voltage levels using a smaller number of switches and transformers, offering a better power quality, less weight, volume, and cost of the system. Moreover, the proposed inverters offer a natural balancing property that can self-regulate the dc-link capacitor voltages. Simulation and experimental results are presented in order to demonstrate the performance and feasibility of the proposed configurations.

Novel Control Scheme for Five-Level Hybrid Flying-Capacitor Inverters Without DC-Link Balancing Circuits

In this article, a novel control scheme for five-level hybrid flying-capacitor inverters is proposed, which can balance the neutral-point voltages across split dc-link capacitors and simultaneously regulate the flying-capacitor voltages.Each capacitor voltage is maintained by regulating the currents that flow through the dc-link neutral points and the flying capacitors. The key components affecting these currents are analyzed to construct a control scheme based on the injection of zero-sequence voltage to the modulation voltage reference.This technique eliminates the need for the auxiliary balancing circuit, which was previously used in the conventional operating schemes to regulate the dc-link capacitor voltages and, thus, reduces the device count and converter volume. The effectiveness of the proposed method for maintaining the capacitor voltages within the allowable range has been verified under various operating conditions through the simulation and experimental results.